diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 9e869a8..7ca62f7 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -11,6 +11,7 @@ from migen import * from litex_boards.platforms import ac701 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -45,12 +46,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = ac701.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -62,10 +63,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT8JTF12864(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 9a4dae7..677453a 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -50,15 +50,15 @@ class CRG(Module): # PCIeSoC ----------------------------------------------------------------------------------------- -class PCIeSoC(SoCSDRAM): - SoCSDRAM.mem_map["csr"] = 0x80000000 - SoCSDRAM.mem_map["rom"] = 0x20000000 +class PCIeSoC(SoCCore): + SoCCore.mem_map["csr"] = 0x80000000 + SoCCore.mem_map["rom"] = 0x20000000 def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, sys_clk_freq, + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Tagus", ident_version=True, **kwargs) @@ -82,10 +82,15 @@ class PCIeSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") - sdram_module = MT41J128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # PCIe ------------------------------------------------------------------------------------- # pcie phy diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 1c6dc14..4157f72 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -11,6 +11,7 @@ from litex_boards.platforms import arty from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -51,12 +52,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = arty.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -69,10 +70,15 @@ class BaseSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq, interface_type = "MEMORY") self.add_csr("ddrphy") - sdram_module = MT41K128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K128M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 0338607..d2518da 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -82,7 +82,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): mem_map = { "hyperram": 0x20000000, } @@ -93,8 +93,8 @@ class BaseSoC(SoCSDRAM): assert sys_clk_freq == int(50e6) platform = c10lprefkit.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -107,10 +107,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = MT48LC16M16(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = MT48LC16M16(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 22e944c..e024c44 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -14,6 +14,7 @@ from litex_boards.platforms import camlink_4k from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -67,13 +68,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, toolchain="trellis", **kwargs): platform = camlink_4k.Platform(toolchain=toolchain) sys_clk_freq = int(81e6) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -86,10 +87,15 @@ class BaseSoC(SoCSDRAM): self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) - sdram_module = MT41K64M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index b9385f2..d6d059f 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import de0nano +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -70,13 +71,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de0nano.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -84,10 +85,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = IS42S16160(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16160(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index 5293c9e..862a2c2 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import de10lite +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -78,13 +79,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de10lite.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -92,10 +93,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = IS42S16320(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16320(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # VGASoC ------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index aceaadd..5c3521f 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -84,13 +84,13 @@ class BaseSoC(SoCCore): # MiSTerSDRAMSoC ----------------------------------------------------------------------------------- -class MiSTerSDRAMSoC(SoCSDRAM): +class MiSTerSDRAMSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de10nano.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, with_sdram=True) @@ -98,10 +98,15 @@ class MiSTerSDRAMSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = AS4C16M16(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = AS4C16M16(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 15c466f..d230c3a 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import de1soc +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -70,13 +71,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de1soc.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -84,11 +85,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - # ISSI IS42S16320D-7TL - sdram_module = IS42S16320(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16320(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index 3623534..6b2e31d 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import de2_115 +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -70,13 +71,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de2_115.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -84,10 +85,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = IS42S16320(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16320(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index c9fa450..3a5ada5 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -10,6 +10,7 @@ from migen import * from litex_boards.platforms import genesys2 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -40,12 +41,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = genesys2.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -57,10 +58,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41J256M16(self.clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41J256M16(self.clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index c754735..d1fff8b 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -17,6 +17,7 @@ from litex_boards.platforms import hadbadge from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -49,12 +50,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs): platform = hadbadge.Platform(toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore --------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -62,10 +63,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) - sdram_module = AS4C32M8(sys_clk_freq, "1:1") - self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = AS4C32M8(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index 930ceb8..da933a3 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -12,6 +12,7 @@ from migen import * from litex_boards.platforms import kc705 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -42,12 +43,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kc705.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -61,10 +62,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 1) self.add_csr("ddrphy") self.add_constant("DDRPHY_CMD_DELAY", 13) - sdram_module = MT8JTF12864(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index c5584bb..48d722e 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -10,6 +10,7 @@ from migen import * from litex_boards.platforms import kcu105 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -49,12 +50,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kcu105.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -68,10 +69,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) - sdram_module = EDY4016A(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = EDY4016A(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index c7d3950..3c3e101 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -10,6 +10,7 @@ from migen import * from litex.boards.platforms import kx2 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -39,12 +40,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kx2.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -56,10 +57,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = H5TC4G63CFR(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = H5TC4G63CFR(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index e1d6e13..946f229 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -9,6 +9,7 @@ from migen import * from litex_boards.platforms import linsn_rv901t +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import S6PLL @@ -45,21 +46,29 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, **kwargs): platform = linsn_rv901t.Platform() sys_clk_freq = int(75e6) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = M12L64322A(sys_clk_freq, "1:1") - self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) + if not self.integrated_main_ram_size: + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.add_sdram("sdram", + phy = self.sdrphy, + module = M12L64322A(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 3d0a1d4..9e13b18 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -11,6 +11,7 @@ from migen.genlib.io import CRG from litex_boards.platforms import mercury_xu5 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -47,12 +48,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = mercury_xu5.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -66,10 +67,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) - sdram_module = MT40A256M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT40A256M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index 30c422b..4859298 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -12,6 +12,7 @@ from litex_boards.platforms import mimas_a7 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -44,12 +45,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = mimas_a7.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -61,10 +62,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41J128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 6a74092..9fa596a 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -14,6 +14,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import minispartan6 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -43,13 +44,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(80e6), **kwargs): assert sys_clk_freq == int(80e6) platform = minispartan6.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -57,10 +58,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = AS4C16M16(sys_clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = AS4C16M16(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 5f6df91..a0c6293 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -49,15 +49,15 @@ class CRG(Module): # PCIeSoC ----------------------------------------------------------------------------------------- -class PCIeSoC(SoCSDRAM): - SoCSDRAM.mem_map["csr"] = 0x80000000 - SoCSDRAM.mem_map["rom"] = 0x20000000 +class PCIeSoC(SoCCore): + SoCCore.mem_map["csr"] = 0x80000000 + SoCCore.mem_map["rom"] = 0x20000000 def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, sys_clk_freq, + # SoCCore --------------------_------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Nereid", ident_version=True, **kwargs) @@ -81,10 +81,15 @@ class PCIeSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") - sdram_module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # PCIe ------------------------------------------------------------------------------------- # pcie phy diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 94d2750..8cfe4f4 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -10,6 +10,7 @@ from migen import * from litex_boards.platforms import netv2 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -45,12 +46,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = netv2.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ------------------------------------------------------------------------------_--- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -62,10 +63,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = K4B2G1646F(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = K4B2G1646F(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index a4a9e85..75a490c 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -10,6 +10,7 @@ from migen import * from litex_boards.platforms import nexys4ddr from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -44,12 +45,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(75e6), **kwargs): platform = nexys4ddr.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ----------------------------------_----------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -61,10 +62,15 @@ class BaseSoC(SoCSDRAM): nphases = 2, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT47H64M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT47H64M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 57cca43..6b693da 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -10,6 +10,7 @@ from migen import * from litex_boards.platforms import nexys_video from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -44,12 +45,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -61,10 +62,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41K256M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K256M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 5e3bb69..5a5a613 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -13,6 +13,7 @@ from litex_boards.platforms import orangecrab from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -74,27 +75,33 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ----------------------------------------------------------------_----------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- - self.submodules.ddrphy = ECP5DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) - self.comb += self.crg.stop.eq(self.ddrphy.init.stop) - sdram_module = MT41K64M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + if not self.integrated_main_ram_size: + self.submodules.ddrphy = ECP5DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") + self.add_constant("ECP5DDRPHY", None) + self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py index c6ce8c8..9298ac9 100755 --- a/litex_boards/targets/pipistrello.py +++ b/litex_boards/targets/pipistrello.py @@ -16,6 +16,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import pipistrello +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -146,33 +147,39 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, **kwargs): sys_clk_freq = (83 + Fraction(1, 3))*1000*1000 platform = pipistrello.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore -----------------------------------------------------------------_---------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) # LPDDR SDRAM ------------------------------------------------------------------------------ - self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"), - memtype = "LPDDR", - rd_bitslip = 1, - wr_bitslip = 3, - dqs_ddr_alignment = "C1") - self.comb += [ - self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), - self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), - ] - self.add_csr("ddrphy") - sdram_module = MT46H32M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"), + memtype = "LPDDR", + rd_bitslip = 1, + wr_bitslip = 3, + dqs_ddr_alignment = "C1") + self.comb += [ + self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), + self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), + ] + self.add_csr("ddrphy") + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT46H32M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index 5fbaa0b..54da125 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -51,15 +51,15 @@ class CRG(Module): # PCIeSoC ----------------------------------------------------------------------------------------- -class PCIeSoC(SoCSDRAM): - SoCSDRAM.mem_map["csr"] = 0x80000000 - SoCSDRAM.mem_map["rom"] = 0x20000000 +class PCIeSoC(SoCCore): + SoCCore.mem_map["csr"] = 0x80000000 + SoCCore.mem_map["rom"] = 0x20000000 def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, sys_clk_freq, + # SoCCore ---------------------------------------------------_------------------------------ + SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Tagus", ident_version=True, **kwargs) @@ -83,10 +83,15 @@ class PCIeSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") - sdram_module = MT41J128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # PCIe ------------------------------------------------------------------------------------- # pcie phy diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index d3f44e7..dde153a 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -82,8 +82,8 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs): platform = trellisboard.Platform(toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore -----------------------------------------------------------------_---------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 8f758dd..ce0ddcd 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -15,6 +15,7 @@ from litex_boards.platforms import ulx3s from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -51,13 +52,14 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, device="LFE5U-45F", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -65,17 +67,22 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) - sdram_module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1") - self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + help="gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--sys-clk-freq", default=50e6, diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index fe9c499..6ad60d7 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -12,6 +12,7 @@ from migen import * from litex_boards.platforms import vc707 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -39,12 +40,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = vc707.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ------------------------------------------------------------------_--------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -56,10 +57,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT8JTF12864(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 66ff5b1..3d2ab93 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -11,6 +11,7 @@ from migen import * from litex_boards.platforms import vcu118 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -47,12 +48,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = vcu118.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ----------------------------------------------------------_----------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -66,10 +67,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) - sdram_module = EDY4016A(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = EDY4016A(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index dc3bb59..b5be138 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -14,6 +14,7 @@ from litex_boards.platforms import versa_ecp5 from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -71,12 +72,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore -----------------------------------------_---------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -89,10 +90,15 @@ class BaseSoC(SoCSDRAM): self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) - sdram_module = MT41K64M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 6440ba6..5a35687 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -11,6 +11,7 @@ from migen import * from litex_boards.platforms import zcu104 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -46,12 +47,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = zcu104.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore -------------------------------------------------------------------------_-------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -65,10 +66,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 1) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) - sdram_module = KVR21SE15S84(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = KVR21SE15S84(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build --------------------------------------------------------------------------------------------