diff --git a/litex_boards/platforms/ac701.py b/litex_boards/platforms/ac701.py index 1a0f37c..1417d9d 100644 --- a/litex_boards/platforms/ac701.py +++ b/litex_boards/platforms/ac701.py @@ -103,6 +103,16 @@ _io = [ Subsignal("tx_n", Pins("C10")) ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")), + Subsignal("clk_p", Pins("F11")), + Subsignal("clk_n", Pins("E11")), + Subsignal("rx_p", Pins("D12 B13 D14 B11")), + Subsignal("rx_n", Pins("C12 A13 C14 A11")), + Subsignal("tx_p", Pins("D10 B9 D8 B7")), + Subsignal("tx_n", Pins("C10 A9 C8 A7")) + ), + # GTP RefClk ("gtp_refclk", 0, Subsignal("p", Pins("AA13")), diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index c4085ff..7accf14 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -4,7 +4,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2019 Vamsi K Vytla -# Copyright (c) 2019 Florent Kermarrec +# Copyright (c) 2019-2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -28,6 +28,9 @@ from liteeth.phy.a7_gtp import QPLLSettings, QPLL from liteeth.phy.a7_1000basex import A7_1000BASEX from liteeth.phy.s7rgmii import LiteEthPHYRGMII +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -53,7 +56,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, ethernet_phy="rgmii", **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, ethernet_phy="rgmii", with_pcie=False, **kwargs): platform = ac701.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -121,6 +124,14 @@ class BaseSoC(SoCCore): self.add_ethernet(phy=self.ethphy) + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_csr("pcie_phy") + self.add_pcie(phy=self.pcie_phy, ndmas=1) + # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), @@ -136,12 +147,21 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY: rgmii (default) or 1000basex") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, ethernet_phy=args.ethernet_phy, **soc_sdram_argdict(args)) + soc = BaseSoC( + with_ethernet = args.with_ethernet, + ethernet_phy = args.ethernet_phy, + with_pcie = args.with_pcie, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index c262aaa..597e770 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -43,9 +43,6 @@ from litedram.modules import MT41K512M16 from litedram.phy import s7ddrphy from litepcie.phy.s7pciephy import S7PCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -108,50 +105,11 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - self.comb += platform.request("pcie_clkreq_n").eq(0) - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - # DMA1 - self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma1") - - self.add_constant("DMA_CHANNELS", 2) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, - "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( @@ -164,24 +122,22 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+") parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) - + soc = BaseSoC(with_pcie = args.with_pcie, **soc_sdram_argdict(args)) if args.with_spi_sdcard: soc.add_spi_sdcard() builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) - if args.driver: generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index aec5a6d..86ceff5 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -4,7 +4,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2018-2019 Rohit Singh -# Copyright (c) 2019 Florent Kermarrec +# Copyright (c) 2019-2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -27,9 +27,6 @@ from litedram.modules import MT41J128M16 from litedram.phy import s7ddrphy from litepcie.phy.s7pciephy import S7PCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -91,41 +88,11 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - self.add_constant("DMA_CHANNELS", 1) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 65c7623..36ad144 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -25,9 +25,6 @@ from litedram.modules import MTA18ASF2G72PZ from litedram.phy import usddrphy from litepcie.phy.usppciephy import USPPCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -97,41 +94,11 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - self.add_constant("DMA_CHANNELS", 1) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index e6aeec8..6087fa5 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -4,7 +4,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2014-2015 Sebastien Bourdeauducq -# Copyright (c) 2014-2019 Florent Kermarrec +# Copyright (c) 2014-2020 Florent Kermarrec # Copyright (c) 2014-2015 Yann Sionneau # SPDX-License-Identifier: BSD-2-Clause @@ -26,6 +26,9 @@ from litedram.phy import s7ddrphy from liteeth.phy import LiteEthPHY +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -49,7 +52,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_sata=False, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_pcie=False, with_sata=False, **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -87,6 +90,14 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_csr("pcie_phy") + self.add_pcie(phy=self.pcie_phy, ndmas=1) + # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins @@ -135,15 +146,25 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args)) + soc = BaseSoC( + with_ethernet = args.with_ethernet, + with_pcie = args.with_pcie, + with_sata = args.with_sata, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index a2eacfa..afa36f5 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -3,7 +3,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2018-2019 Florent Kermarrec +# Copyright (c) 2018-2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -25,6 +25,9 @@ from litedram.phy import usddrphy from liteeth.phy.ku_1000basex import KU_1000BASEX +from litepcie.phy.uspciephy import USPCIEPHY +from litepcie.software import generate_litepcie_software + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -59,7 +62,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, with_pcie=False, **kwargs): platform = kcu105.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -101,6 +104,14 @@ class BaseSoC(SoCCore): if with_etherbone: self.add_etherbone(phy=self.ethphy) + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_csr("pcie_phy") + self.add_pcie(phy=self.pcie_phy, ndmas=1) + # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), @@ -113,18 +124,27 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KCU105") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - builder_args(parser) - soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + builder_args(parser) + soc_sdram_args(parser) args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) - soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, - **soc_sdram_argdict(args)) + soc = BaseSoC( + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index a2f562f..2f7f759 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -4,7 +4,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2018-2019 Rohit Singh -# Copyright (c) 2019 Florent Kermarrec +# Copyright (c) 2019-2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -26,9 +26,6 @@ from litedram.modules import MT8KTF51264 from litedram.phy import s7ddrphy from litepcie.phy.s7pciephy import S7PCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -86,59 +83,30 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - self.add_constant("DMA_CHANNELS", 1) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nereid") parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() platform = nereid.Platform() soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) if args.driver: diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 0ef175b..058a580 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -28,9 +28,6 @@ from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII from litepcie.phy.s7pciephy import S7PCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -103,41 +100,11 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - self.add_constant("DMA_CHANNELS", 1) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( @@ -161,7 +128,11 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + with_ethernet = args.with_ethernet, + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: soc.add_spi_sdcard() @@ -170,7 +141,6 @@ def main(): builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) - if args.driver: generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index 97e4d28..f550ea8 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -4,7 +4,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2018-2019 Rohit Singh -# Copyright (c) 2019 Florent Kermarrec +# Copyright (c) 2019-2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -26,10 +26,8 @@ from litex.soc.cores.led import LedChaser from litedram.modules import MT41J128M16 from litedram.phy import s7ddrphy + from litepcie.phy.s7pciephy import S7PCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -91,41 +89,11 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), - data_width = 64, + data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - self.add_constant("DMA_CHANNELS", 1) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( @@ -139,7 +107,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) @@ -147,7 +115,7 @@ def main(): platform = tagus.Platform() soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) if args.driver: diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 4c1649f..51befd1 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -21,6 +21,10 @@ from litex.soc.cores.led import LedChaser from litedram.modules import MT8JTF12864 from litedram.phy import s7ddrphy + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -44,7 +48,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): platform = vc707.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -73,6 +77,14 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_csr("pcie_phy") + self.add_pcie(phy=self.pcie_phy, ndmas=1) + # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), @@ -83,16 +95,21 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on VC707") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC(with_pcie_=args.with_pcie, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index f246b30..7a284ff 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -24,9 +24,6 @@ from litedram.modules import MT40A512M8 from litedram.phy import usddrphy from litepcie.phy.usppciephy import USPPCIEPHY -from litepcie.core import LitePCIeEndpoint, LitePCIeMSI -from litepcie.frontend.dma import LitePCIeDMA -from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- @@ -95,41 +92,11 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert self.csr_data_width == 32 - # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") - - # Endpoint - self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) - - # Wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, - base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) - - # DMA0 - self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, - with_buffering = True, buffering_depth=1024, - with_loopback = True) - self.add_csr("pcie_dma0") - - self.add_constant("DMA_CHANNELS", 1) - - # MSI - self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") - self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) - self.interrupts = { - "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, - "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, - } - for i, (k, v) in enumerate(sorted(self.interrupts.items())): - self.comb += self.pcie_msi.irqs[i].eq(v) - self.add_constant(k + "_INTERRUPT", i) + self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(