From 84468c2a63697dfe69bab28cd3d6028f4149d2b5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 May 2020 11:51:57 +0200 Subject: [PATCH] targets/CRG: platforms are now automatically constraining the input clocks. --- litex_boards/targets/aller.py | 1 - litex_boards/targets/c10lprefkit.py | 1 - litex_boards/targets/camlink_4k.py | 1 - litex_boards/targets/colorlight_5a_75b.py | 1 - litex_boards/targets/de0nano.py | 1 - litex_boards/targets/de10lite.py | 1 - litex_boards/targets/de10nano.py | 1 - litex_boards/targets/de1soc.py | 1 - litex_boards/targets/de2_115.py | 1 - litex_boards/targets/ecp5_evn.py | 1 - litex_boards/targets/ecpix5.py | 1 - litex_boards/targets/hadbadge.py | 1 - litex_boards/targets/linsn_rv901t.py | 3 --- litex_boards/targets/nereid.py | 1 - litex_boards/targets/orangecrab.py | 1 - litex_boards/targets/tagus.py | 1 - litex_boards/targets/trellisboard.py | 1 - litex_boards/targets/ulx3s.py | 1 - litex_boards/targets/versa_ecp5.py | 1 - 19 files changed, 21 deletions(-) diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 6c06e41..7f4b746 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -48,7 +48,6 @@ class CRG(Module, AutoCSR): # Clk/Rst clk100 = platform.request("clk100") - platform.add_period_constraint(clk100, 1e9/100e6) # Delay software reset by 10us to ensure write has been acked on PCIe. rst_delay = WaitTimer(int(10e-6*sys_clk_freq)) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 6e41ccd..009e863 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -34,7 +34,6 @@ class _CRG(Module): # Clk / Rst clk12 = platform.request("clk12") - platform.add_period_constraint(clk12, 1e9/12e6) # PLL self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-A7") diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 0fbd794..af50330 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -37,7 +37,6 @@ class _CRG(Module): # clk / rst clk27 = platform.request("clk27") - platform.add_period_constraint(clk27, 1e9/27e6) # power on reset por_count = Signal(16, reset=2**16-1) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index 9a4c9c9..d8f7215 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -67,7 +67,6 @@ class _CRG(Module): # Clk / Rst clk25 = platform.request("clk25") rst_n = 1 if not with_rst else platform.request("user_btn_n", 0) - platform.add_period_constraint(clk25, 1e9/25e6) # PLL self.submodules.pll = pll = ECP5PLL() diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 2f8cd47..3a48cfd 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -31,7 +31,6 @@ class _CRG(Module): # Clk / Rst clk50 = platform.request("clk50") - platform.add_period_constraint(clk50, 1e9/50e6) # PLL self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index bdcbd71..ce3917e 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -34,7 +34,6 @@ class _CRG(Module): # Clk / Rst clk50 = platform.request("clk50") - platform.add_period_constraint(clk50, 1e9/50e6) # PLL self.submodules.pll = pll = Max10PLL(speedgrade="-7") diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 878228e..7c63adc 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -31,7 +31,6 @@ class _CRG(Module): # Clk / Rst clk50 = platform.request("clk50") - platform.add_period_constraint(clk50, 1e9/50e6) # PLL self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7") diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 8c1a375..eb445c5 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -31,7 +31,6 @@ class _CRG(Module): # Clk / Rst clk50 = platform.request("clk50") - platform.add_period_constraint(clk50, 1e9/50e6) # PLL self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6") diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index a75b2ba..290c392 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -31,7 +31,6 @@ class _CRG(Module): # Clk / Rst clk50 = platform.request("clk50") - platform.add_period_constraint(clk50, 1e9/50e6) # PLL self.submodules.pll = pll = CycloneIVPLL(speedgrade="-7") diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index 859e9f0..0615cb0 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -25,7 +25,6 @@ class _CRG(Module): # clk / rst clk = clk12 = platform.request("clk12") rst_n = platform.request("rst_n") - platform.add_period_constraint(clk12, 1e9/12e6) if x5_clk_freq is not None: clk = clk50 = platform.request("ext_clk50") self.comb += platform.request("ext_clk50_en").eq(1) diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 66cc2ed..2a0d250 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -39,7 +39,6 @@ class _CRG(Module): # Clk / Rst clk100 = platform.request("clk100") rst_n = platform.request("rst_n") - platform.add_period_constraint(clk100, 1e9/100e6) # Power on reset por_count = Signal(16, reset=2**16-1) diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 629aeb2..6eda0de 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -38,7 +38,6 @@ class _CRG(Module): # Clk / Rst clk8 = platform.request("clk8") - platform.add_period_constraint(clk8, 1e9/8e6) # PLL self.submodules.pll = pll = ECP5PLL() diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index cc8abc0..f948fee 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -32,7 +32,6 @@ class _CRG(Module): # # # clk25 = platform.request("clk25") - platform.add_period_constraint(clk25, 1e9/25e6) self.submodules.pll = pll = S6PLL(speedgrade=-2) pll.register_clkin(clk25, 25e6) @@ -96,8 +95,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index f5831ea..35038f2 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -47,7 +47,6 @@ class CRG(Module, AutoCSR): # Clk/Rst clk100 = platform.request("clk100") - platform.add_period_constraint(clk100, 1e9/100e6) # Delay software reset by 10us to ensure write has been acked on PCIe. rst_delay = WaitTimer(int(10e-6*sys_clk_freq)) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index aa4491b..f5b3e62 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -38,7 +38,6 @@ class _CRG(Module): # Clk / Rst clk48 = platform.request("clk48") - platform.add_period_constraint(clk48, 1e9/48e6) # Power on reset por_count = Signal(16, reset=2**16-1) diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index 89eb333..15dc4ff 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -46,7 +46,6 @@ class CRG(Module, AutoCSR): # Clk/Rst clk100 = platform.request("clk100") - platform.add_period_constraint(clk100, 1e9/100e6) # Delay software reset by 10us to ensure write has been acked on PCIe. rst_delay = WaitTimer(int(10e-6*sys_clk_freq)) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index fc979bf..73db1a9 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -39,7 +39,6 @@ class _CRG(Module): # Clk / Rst clk12 = platform.request("clk12") rst = platform.request("user_btn", 0) - platform.add_period_constraint(clk12, 1e9/12e6) # Power on reset por_count = Signal(16, reset=2**16-1) diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index dd4f237..e0bbf4c 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -36,7 +36,6 @@ class _CRG(Module): # Clk / Rst clk25 = platform.request("clk25") rst = platform.request("rst") - platform.add_period_constraint(clk25, 1e9/25e6) # PLL self.submodules.pll = pll = ECP5PLL() diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 48e6eb9..6618093 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -40,7 +40,6 @@ class _CRG(Module): # Clk / Rst clk100 = platform.request("clk100") rst_n = platform.request("rst_n") - platform.add_period_constraint(clk100, 1e9/100e6) # Power on reset por_count = Signal(16, reset=2**16-1)