diff --git a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py
index b02170d..837895d 100644
--- a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py
+++ b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py
@@ -14,7 +14,6 @@ from litex.build.efinix import EfinixProgrammer
 _io = [
     # Clk
     ("clk40", 0, Pins("P19"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
-    ("clk50", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
 
     # Leds
     ("user_led", 0, Pins("AB16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
@@ -90,6 +89,10 @@ _io = [
         Subsignal("mdio",    Pins("D24")),
         IOStandard("3.3_V_LVTTL_/_LVCMOS")
     ),
+
+    # DRAM.
+    ("br0_pll_clkin", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
+    ("br1_pll_clkin", 0, Pins("AA9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
 ]
 
 # Connectors ---------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
index fab7d74..c9adf70 100755
--- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
+++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
@@ -114,7 +114,7 @@ class BaseSoC(SoCCore):
         if False:
             # DRAM / PLL Blocks.
             # ------------------
-            dram_clk = platform.request("clk50")
+            dram_clk = platform.request("br0_pll_clkin")
             platform.toolchain.excluded_ios.append(dram_clk)
 
             block = {"type" : "DRAM"}
@@ -124,8 +124,8 @@ class BaseSoC(SoCCore):
 
             # DRAM Rst.
             # ---------
-            pll_dram_rstn = platform.add_iface_io("pll_dram_rstn")
-            self.comb += pll_dram_rstn.eq(platform.request("user_btn", 1))
+            br0_pll_rstn = platform.add_iface_io("br0_pll_rstn")
+            self.comb += br0_pll_rstn.eq(platform.request("user_btn", 1))
             self.specials += Instance("ddr_reset_sequencer",
                  i_ddr_rstn_i        = ~ResetSignal("sys"),
                  i_clk               = ClockSignal("sys"),