diff --git a/litex_boards/platforms/ecpix5.py b/litex_boards/platforms/ecpix5.py
index 88e3b22..07f0be6 100644
--- a/litex_boards/platforms/ecpix5.py
+++ b/litex_boards/platforms/ecpix5.py
@@ -67,6 +67,23 @@ _io = [
         Subsignal("odt",   Pins("P3"), IOStandard("SSTL15_I")),
         Misc("SLEWRATE=FAST"),
     ),
+
+    # ethernet
+    ("eth_clocks", 0,
+        Subsignal("tx", Pins("A12")),
+        Subsignal("rx", Pins("E11")),
+        IOStandard("LVCMOS33")
+    ),
+    ("eth", 0,
+        Subsignal("rst_n",   Pins("C13")),
+        Subsignal("mdio",    Pins("A13")),
+        Subsignal("mdc",     Pins("C11")),
+        Subsignal("rx_ctl",  Pins("A11")),
+        Subsignal("rx_data", Pins("B11 A10 B10 A9")),
+        Subsignal("tx_ctl",  Pins("C9")),
+        Subsignal("tx_data", Pins("D8 C8 B8 A8")),
+        IOStandard("LVCMOS33")
+    ),
 ]
 
 _connectors = []
diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py
index 0dd7dec..1d4ed8b 100755
--- a/litex_boards/targets/ecpix5.py
+++ b/litex_boards/targets/ecpix5.py
@@ -20,6 +20,8 @@ from litex.soc.integration.builder import *
 from litedram.modules import MT41K256M16
 from litedram.phy import ECP5DDRPHY
 
+from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -69,7 +71,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
         platform = ecpix5.Platform(toolchain="trellis")
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -95,6 +97,14 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Ethernet ---------------------------------------------------------------------------------
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHYRGMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
+
         # Leds (Disable...) ------------------------------------------------------------------------
         for i in range(4):
             rgb_led_pads = platform.request("rgb_led", i)
@@ -127,13 +137,14 @@ def main():
     builder_args(parser)
     soc_core_args(parser)
     trellis_args(parser)
+    parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
     parser.add_argument("--load", action="store_true", help="load bitstream")
     args = parser.parse_args()
 
     if args.load:
         load()
 
-    soc     = BaseSoC(**soc_core_argdict(args))
+    soc     = BaseSoC(with_ethernet=with_ethernet, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(**trellis_argdict(args))