diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index 0ab0434..d8b6af4 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -145,14 +145,14 @@ def main():
     parser.add_argument("--load",                action="store_true", help="Load bitstream")
     parser.add_argument("--flash",               action="store_true", help="Flash Bitstream")
     parser.add_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency (default: 24MHz)")
-    parser.add_argument("--bios-flash-offset",   default=0x40000,     help="BIOS offset in SPI Flash (default: 0x40000)")
+    parser.add_argument("--bios-flash-offset",   default="0x40000",   help="BIOS offset in SPI Flash (default: 0x40000)")
     parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (with DVI PMOD)")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset   = args.bios_flash_offset,
+        bios_flash_offset   = int(args.bios_flash_offset, 0),
         sys_clk_freq        = int(float(args.sys_clk_freq)),
         with_video_terminal = args.with_video_terminal,
         **soc_core_argdict(args)
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index 65c8956..c78bc6c 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -119,14 +119,14 @@ def main():
     parser.add_argument("--build",               action="store_true", help="Build bitstream")
     parser.add_argument("--flash",               action="store_true", help="Flash bitstream and bios")
     parser.add_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency (default: 24MHz)")
-    parser.add_argument("--bios-flash-offset",   default=0xa0000,     help="BIOS offset in SPI Flash (default: 0xa0000)")
+    parser.add_argument("--bios-flash-offset",   default="0xa0000",   help="BIOS offset in SPI Flash (default: 0xa0000)")
     parser.add_argument("--revision",            default="v1",        help="Board revision 'v0' or 'v1'")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset   = args.bios_flash_offset,
+        bios_flash_offset   = int(args.bios_flash_offset, 0),
         sys_clk_freq        = int(float(args.sys_clk_freq)),
 		revision            = args.revision,
         **soc_core_argdict(args)
diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py
index 7c4f405..354816f 100755
--- a/litex_boards/targets/efinix_xyloni_dev_kit.py
+++ b/litex_boards/targets/efinix_xyloni_dev_kit.py
@@ -88,18 +88,18 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Xyloni Dev Kit")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
-    parser.add_argument("--sys-clk-freq",      default=33.333e6, help="System clock frequency (default: 33.333MHz)")
-    parser.add_argument("--bios-flash-offset", default=0x40000,  help="BIOS offset in SPI Flash (default: 0x40000)")
+    parser.add_argument("--build", action="store_true",           help="Build bitstream")
+    parser.add_argument("--load",  action="store_true",           help="Load bitstream")
+    parser.add_argument("--flash", action="store_true",           help="Flash Bitstream")
+    parser.add_argument("--sys-clk-freq",      default=33.333e6,  help="System clock frequency (default: 33.333MHz)")
+    parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash (default: 0x40000)")
 
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset = args.bios_flash_offset,
+        bios_flash_offset = int(args.bios_flash_offset, 0),
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py
index a197fed..5795b53 100755
--- a/litex_boards/targets/jungle_electronics_fireant.py
+++ b/litex_boards/targets/jungle_electronics_fireant.py
@@ -103,18 +103,18 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Jungle Electronics FireAnt")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
-    parser.add_argument("--sys-clk-freq",      default=33.333e6, help="System clock frequency (default: 33.333MHz)")
-    parser.add_argument("--bios-flash-offset", default=0x40000,  help="BIOS offset in SPI Flash (default: 0x40000)")
+    parser.add_argument("--build", action="store_true",           help="Build bitstream")
+    parser.add_argument("--load",  action="store_true",           help="Load bitstream")
+    parser.add_argument("--flash", action="store_true",           help="Flash Bitstream")
+    parser.add_argument("--sys-clk-freq",      default=33.333e6,  help="System clock frequency (default: 33.333MHz)")
+    parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash (default: 0x40000)")
 
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset = args.bios_flash_offset,
+        bios_flash_offset = int(args.bios_flash_offset, 0),
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index af79c5b..61a1c69 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -170,7 +170,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--sys-clk-freq",      default=12e6,        help="System clock frequency (default: 12MHz)")
-    parser.add_argument("--bios-flash-offset", default=0x20000,     help="BIOS offset in SPI Flash (default: 0x20000)")
+    parser.add_argument("--bios-flash-offset", default="0x20000",   help="BIOS offset in SPI Flash (default: 0x20000)")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream")
     builder_args(parser)
     soc_core_args(parser)
@@ -179,7 +179,7 @@ def main():
     dfu_flash_offset = 0x40000
 
     soc = BaseSoC(
-        bios_flash_offset = dfu_flash_offset + args.bios_flash_offset,
+        bios_flash_offset = dfu_flash_offset + int(args.bios_flash_offset, 0),
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args)
     )
@@ -187,7 +187,7 @@ def main():
     builder.build(run=args.build)
 
     if args.flash:
-        flash(builder.output_dir, soc.build_name, args.bios_flash_offset)
+        flash(builder.output_dir, soc.build_name, int(args.bios_flash_offset, 0))
 
 if __name__ == "__main__":
     main()
diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index ae9e166..55068c7 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -149,14 +149,14 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--sys-clk-freq",      default=12e6,        help="System clock frequency (default: 12MHz)")
-    parser.add_argument("--bios-flash-offset", default=0x20000,     help="BIOS offset in SPI Flash (default: 0x20000)")
+    parser.add_argument("--bios-flash-offset", default="0x20000",   help="BIOS offset in SPI Flash (default: 0x20000)")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset = args.bios_flash_offset,
+        bios_flash_offset = int(args.bios_flash_offset, 0),
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args)
     )
diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py
index cc6c920..fc3c4e3 100755
--- a/litex_boards/targets/muselab_icesugar.py
+++ b/litex_boards/targets/muselab_icesugar.py
@@ -118,13 +118,13 @@ def main():
     parser.add_argument("--load",                action="store_true", help="Load bitstream")
     parser.add_argument("--flash",               action="store_true", help="Flash Bitstream")
     parser.add_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency (default: 24MHz)")
-    parser.add_argument("--bios-flash-offset",   default=0x40000,     help="BIOS offset in SPI Flash (default: 0x40000)")
+    parser.add_argument("--bios-flash-offset",   default="0x40000",   help="BIOS offset in SPI Flash (default: 0x40000)")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset   = args.bios_flash_offset,
+        bios_flash_offset   = int(args.bios_flash_offset, 0),
         sys_clk_freq        = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args)
     )
@@ -136,7 +136,7 @@ def main():
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
 
     if args.flash:
-        flash(args.bios_flash_offset)
+        flash(int(args.bios_flash_offset, 0))
 
 if __name__ == "__main__":
     main()
diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py
index 06f84cd..8b21d88 100755
--- a/litex_boards/targets/qwertyembedded_beaglewire.py
+++ b/litex_boards/targets/qwertyembedded_beaglewire.py
@@ -78,7 +78,7 @@ class BaseSoC(SoCCore):
         kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, sys_clk_freq, 
+        SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on Beaglewire",
             ident_version  = True,
             **kwargs)
@@ -115,16 +115,14 @@ class BaseSoC(SoCCore):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Beaglewire")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
-    parser.add_argument("--bios-flash-offset", default=0x60000,     help="BIOS offset in SPI Flash (default: 0x60000)")
+    parser.add_argument("--bios-flash-offset", default="0x60000",   help="BIOS offset in SPI Flash (default: 0x60000)")
     parser.add_argument("--sys-clk-freq",      default=50e6,        help="System clock frequency (default: 50MHz)")
-    parser.add_argument("--output_dir",        default="build",         help="Output directory of csr")
-    parser.add_argument("--csr_csv",           default="build/csr.csv", help="csr.csv")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-         bios_flash_offset = args.bios_flash_offset,
+         bios_flash_offset = int(args.bios_flash_offset, 0),
          sys_clk_freq      = int(float(args.sys_clk_freq)),
          **soc_core_argdict(args)
     )
diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py
index ba864fe..40600d6 100755
--- a/litex_boards/targets/tinyfpga_bx.py
+++ b/litex_boards/targets/tinyfpga_bx.py
@@ -69,14 +69,14 @@ class BaseSoC(SoCCore):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA BX")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
-    parser.add_argument("--bios-flash-offset", default=0x50000,     help="BIOS offset in SPI Flash (default: 0x50000)")
+    parser.add_argument("--bios-flash-offset", default="0x50000",   help="BIOS offset in SPI Flash (default: 0x50000)")
     parser.add_argument("--sys-clk-freq",      default=16e6,        help="System clock frequency (default: 16MHz)")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
-         bios_flash_offset = args.bios_flash_offset,
+         bios_flash_offset = int(args.bios_flash_offset, 0),
          sys_clk_freq      = int(float(args.sys_clk_freq)),
          **soc_core_argdict(args)
     )
diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py
index 6b240fd..8283f46 100755
--- a/litex_boards/targets/trenz_tec0117.py
+++ b/litex_boards/targets/trenz_tec0117.py
@@ -160,7 +160,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on TEC0117")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--load",              action="store_true", help="Load bitstream")
-    parser.add_argument("--bios-flash-offset", default=0x0000,      help="BIOS offset in SPI Flash (0x00000 default)")
+    parser.add_argument("--bios-flash-offset", default="0x0000",    help="BIOS offset in SPI Flash (0x00000 default)")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream and BIOS")
     parser.add_argument("--sys-clk-freq",      default=25e6,        help="System clock frequency (default: 25MHz)")
     sdopts = parser.add_mutually_exclusive_group()
@@ -171,7 +171,7 @@ def main():
     args = parser.parse_args()
 
     soc = BaseSoC(
-        bios_flash_offset = args.bios_flash_offset,
+        bios_flash_offset = int(args.bios_flash_offset, 0),
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args)
     )
@@ -191,7 +191,7 @@ def main():
     if args.flash:
         prog = soc.platform.create_programmer()
         prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
-        flash(args.bios_flash_offset)
+        flash(int(args.bios_flash_offset, 0))
 
 if __name__ == "__main__":
     main()