From 867489d8555245d9f07bddb438cefe11414eb667 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 Apr 2022 10:01:06 +0200 Subject: [PATCH] xilinx_zcu106: Add PCIe Gen3 X4 support. --- litex_boards/platforms/xilinx_zcu106.py | 29 +++++++++++++++++++++++++ litex_boards/targets/xilinx_zcu106.py | 15 ++++++++++++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/xilinx_zcu106.py b/litex_boards/platforms/xilinx_zcu106.py index f5348c7..08c0bc0 100644 --- a/litex_boards/platforms/xilinx_zcu106.py +++ b/litex_boards/platforms/xilinx_zcu106.py @@ -43,6 +43,35 @@ _io = [ IOStandard("LVCMOS12") ), + # PCIe + ("pcie_x1", 0, + Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("AB8")), + Subsignal("clk_n", Pins("AB7")), + Subsignal("rx_p", Pins("AE2")), + Subsignal("rx_n", Pins("AE1")), + Subsignal("tx_p", Pins("AD4")), + Subsignal("tx_n", Pins("AD3")), + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("AB8")), + Subsignal("clk_n", Pins("AB7")), + Subsignal("rx_p", Pins("AE2 AF4")), + Subsignal("rx_n", Pins("AE1 AF3")), + Subsignal("tx_p", Pins("AD4 AE6")), + Subsignal("tx_n", Pins("AD3 AE5")), + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("AB8")), + Subsignal("clk_n", Pins("AB7")), + Subsignal("rx_p", Pins("AE2 AF4 AG2 AJ2")), + Subsignal("rx_n", Pins("AE1 AF3 AG1 AJ1")), + Subsignal("tx_p", Pins("AD4 AE6 AG6 AH4")), + Subsignal("tx_n", Pins("AD3 AE5 AG5 AH3")), + ), + # DDR4 SDRAM ("ddram", 0, Subsignal("a", Pins( diff --git a/litex_boards/targets/xilinx_zcu106.py b/litex_boards/targets/xilinx_zcu106.py index 723ce04..6fff9d9 100755 --- a/litex_boards/targets/xilinx_zcu106.py +++ b/litex_boards/targets/xilinx_zcu106.py @@ -19,6 +19,9 @@ from litex.soc.cores.led import LedChaser from litedram.modules import MT40A256M16 from litedram.phy import usddrphy +from litepcie.phy.usppciephy import USPPCIEPHY +from litepcie.software import generate_litepcie_software + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -54,7 +57,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs): platform = zcu106.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -78,6 +81,14 @@ class BaseSoC(SoCCore): l2_cache_size = kwargs.get("l2_size", 8192) ) + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), + speed = "gen3", + data_width = 128, + bar0_size = 0x20000) + self.add_pcie(phy=self.pcie_phy, ndmas=1) + # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( @@ -93,12 +104,14 @@ def main(): target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") + target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args))