diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
index 1a98ab9..6858f94 100755
--- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
+++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
@@ -112,8 +112,6 @@ class BaseSoC(SoCCore):
 
         # LPDDR3 SDRAM -----------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
-            #./efinix_trion_t120_bga576_dev_kit.py --with-lpddr3 --sys-clk-freq=50e6 --csr-csv=csr.csv --build --load
-
             # DRAM / PLL Blocks.
             # ------------------
             br0_pll_clkin = platform.request("br0_pll_clkin")