From 877bc4b45e13a73093e9876302c72d9e1b4ac019 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 May 2022 12:42:04 +0200 Subject: [PATCH] targets: Use full imports (vendor_board). --- litex_boards/targets/aliexpress_stlv7325.py | 4 ++-- litex_boards/targets/aliexpress_xc7k420t.py | 4 ++-- litex_boards/targets/alinx_ax7010.py | 4 ++-- .../targets/antmicro_datacenter_ddr4_test_board.py | 4 ++-- litex_boards/targets/antmicro_lpddr4_test_board.py | 4 ++-- litex_boards/targets/decklink_intensity_pro_4k.py | 4 ++-- litex_boards/targets/decklink_mini_4k.py | 4 ++-- litex_boards/targets/decklink_quad_hdmi_recorder.py | 4 ++-- litex_boards/targets/digilent_arty.py | 10 +++++----- litex_boards/targets/digilent_arty_s7.py | 4 ++-- litex_boards/targets/digilent_atlys.py | 4 ++-- litex_boards/targets/digilent_basys3.py | 6 +++--- litex_boards/targets/digilent_genesys2.py | 4 ++-- litex_boards/targets/digilent_nexys4ddr.py | 4 ++-- litex_boards/targets/digilent_nexys_video.py | 4 ++-- litex_boards/targets/digilent_pynq_z1.py | 4 ++-- litex_boards/targets/enclustra_mercury_kx2.py | 4 ++-- litex_boards/targets/enclustra_mercury_xu5.py | 4 ++-- litex_boards/targets/gsd_butterstick.py | 6 +++--- litex_boards/targets/gsd_orangecrab.py | 4 ++-- litex_boards/targets/hackaday_hadbadge.py | 4 ++-- litex_boards/targets/kosagi_fomu.py | 4 ++-- litex_boards/targets/kosagi_netv2.py | 4 ++-- litex_boards/targets/krtkl_snickerdoodle.py | 6 +++--- litex_boards/targets/lambdaconcept_ecpix5.py | 4 ++-- litex_boards/targets/lattice_crosslink_nx_evn.py | 6 +++--- litex_boards/targets/lattice_crosslink_nx_vip.py | 6 ++---- litex_boards/targets/lattice_ecp5_evn.py | 4 ++-- litex_boards/targets/lattice_ecp5_vip.py | 4 ++-- litex_boards/targets/lattice_versa_ecp5.py | 4 ++-- litex_boards/targets/myminieye_runber.py | 4 ++-- litex_boards/targets/numato_aller.py | 4 ++-- litex_boards/targets/numato_mimas_a7.py | 4 ++-- litex_boards/targets/numato_nereid.py | 4 ++-- litex_boards/targets/numato_tagus.py | 4 ++-- litex_boards/targets/qwertyembedded_beaglewire.py | 4 ++-- litex_boards/targets/radiona_ulx3s.py | 4 ++-- litex_boards/targets/rz_easyfpga.py | 4 ++-- litex_boards/targets/saanlima_pipistrello.py | 4 ++-- litex_boards/targets/scarabhardware_minispartan6.py | 4 ++-- .../targets/seeedstudio_spartan_edge_accelerator.py | 4 ++-- litex_boards/targets/siglent_sds1104xe.py | 4 ++-- litex_boards/targets/sipeed_tang_nano.py | 7 +++---- litex_boards/targets/sipeed_tang_nano_4k.py | 7 +++---- litex_boards/targets/sipeed_tang_nano_9k.py | 5 ++--- litex_boards/targets/sipeed_tang_primer.py | 2 +- litex_boards/targets/sqrl_acorn.py | 6 +++--- litex_boards/targets/sqrl_fk33.py | 4 ++-- litex_boards/targets/sqrl_xcu1525.py | 4 ++-- litex_boards/targets/terasic_de0nano.py | 4 ++-- litex_boards/targets/terasic_de10lite.py | 4 ++-- litex_boards/targets/terasic_de10nano.py | 4 ++-- litex_boards/targets/terasic_de1soc.py | 4 ++-- litex_boards/targets/terasic_de2_115.py | 4 ++-- litex_boards/targets/terasic_deca.py | 4 ++-- litex_boards/targets/trenz_c10lprefkit.py | 4 ++-- litex_boards/targets/trenz_cyc1000.py | 4 ++-- litex_boards/targets/trenz_max1000.py | 4 ++-- litex_boards/targets/trenz_tec0117.py | 10 +++++----- litex_boards/targets/tul_pynq_z2.py | 4 ++-- litex_boards/targets/xilinx_ac701.py | 4 ++-- litex_boards/targets/xilinx_alveo_u250.py | 4 ++-- litex_boards/targets/xilinx_alveo_u280.py | 4 ++-- litex_boards/targets/xilinx_kc705.py | 4 ++-- litex_boards/targets/xilinx_kcu105.py | 4 ++-- litex_boards/targets/xilinx_vc707.py | 4 ++-- litex_boards/targets/xilinx_vcu118.py | 4 ++-- litex_boards/targets/xilinx_zcu102.py | 4 ++-- litex_boards/targets/xilinx_zcu104.py | 4 ++-- litex_boards/targets/xilinx_zcu106.py | 4 ++-- litex_boards/targets/xilinx_zcu216.py | 1 + litex_boards/targets/xilinx_zybo_z7.py | 5 +++-- 72 files changed, 156 insertions(+), 159 deletions(-) diff --git a/litex_boards/targets/aliexpress_stlv7325.py b/litex_boards/targets/aliexpress_stlv7325.py index f1b8813..932a01b 100755 --- a/litex_boards/targets/aliexpress_stlv7325.py +++ b/litex_boards/targets/aliexpress_stlv7325.py @@ -13,7 +13,7 @@ import os from migen import * -from litex_boards.platforms import stlv7325 +from litex_boards.platforms import aliexpress_stlv7325 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -64,7 +64,7 @@ class BaseSoC(SoCCore): with_pcie = False, with_sata = False, **kwargs): - platform = stlv7325.Platform() + platform = aliexpress_stlv7325.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/aliexpress_xc7k420t.py b/litex_boards/targets/aliexpress_xc7k420t.py index a7a46b0..f7c9223 100755 --- a/litex_boards/targets/aliexpress_xc7k420t.py +++ b/litex_boards/targets/aliexpress_xc7k420t.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import xc7k420t +from litex_boards.platforms import aliexpress_xc7k420t from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * @@ -38,7 +38,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs): - platform = xc7k420t.Platform() + platform = aliexpress_xc7k420t.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/alinx_ax7010.py b/litex_boards/targets/alinx_ax7010.py index 0d3a47c..6038228 100755 --- a/litex_boards/targets/alinx_ax7010.py +++ b/litex_boards/targets/alinx_ax7010.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import ax7010 +from litex_boards.platforms import alinx_ax7010 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.interconnect import axi @@ -36,7 +36,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs): - platform = ax7010.Platform() + platform = alinx_ax7010.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 7009194..af3ed39 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -11,7 +11,7 @@ import json from migen import * -from litex_boards.platforms import datacenter_ddr4_test_board +from litex_boards.platforms import antmicro_datacenter_ddr4_test_board from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -77,7 +77,7 @@ class BaseSoC(SoCCore): with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_reset_time="10e-3", eth_dynamic_ip=False, with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, with_spi_flash=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs): - platform = datacenter_ddr4_test_board.Platform() + platform = antmicro_datacenter_ddr4_test_board.Platform() # CRG -------------------------------------------------------------------------------------- with_video_pll = (with_video_terminal or with_video_framebuffer) diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index 2d4bfd2..91f103d 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -7,7 +7,7 @@ from migen import * -from litex_boards.platforms import lpddr4_test_board +from litex_boards.platforms import antmicro_lpddr4_test_board from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -49,7 +49,7 @@ class BaseSoC(SoCCore): with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, with_led_chaser=True, **kwargs): - platform = lpddr4_test_board.Platform() + platform = antmicro_lpddr4_test_board.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq) diff --git a/litex_boards/targets/decklink_intensity_pro_4k.py b/litex_boards/targets/decklink_intensity_pro_4k.py index aa40e64..9734764 100755 --- a/litex_boards/targets/decklink_intensity_pro_4k.py +++ b/litex_boards/targets/decklink_intensity_pro_4k.py @@ -12,7 +12,7 @@ import os from migen import * -from litex_boards.platforms import intensity_pro_4k +from litex_boards.platforms import decklink_intensity_pro_4k from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -41,7 +41,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): - platform = intensity_pro_4k.Platform() + platform = decklink_intensity_pro_4k.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/decklink_mini_4k.py b/litex_boards/targets/decklink_mini_4k.py index 09f7dfe..204355b 100755 --- a/litex_boards/targets/decklink_mini_4k.py +++ b/litex_boards/targets/decklink_mini_4k.py @@ -14,7 +14,7 @@ import os from migen import * -from litex_boards.platforms import mini_4k +from litex_boards.platforms import decklink_mini_4k from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -74,7 +74,7 @@ class BaseSoC(SoCMini): def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs): if with_video_terminal or with_video_framebuffer: sys_clk_freq = int(148.5e6) # FIXME: For now requires sys_clk >= video_clk. - platform = mini_4k.Platform() + platform = decklink_mini_4k.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index a4de145..4cf2f2d 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -17,7 +17,7 @@ import os from migen import * -from litex_boards.platforms import quad_hdmi_recorder +from litex_boards.platforms import decklink_quad_hdmi_recorder from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -59,7 +59,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, pcie_lanes=4, **kwargs): - platform = quad_hdmi_recorder.Platform() + platform = decklink_quad_hdmi_recorder.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 5bb1cba..322032c 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -13,7 +13,7 @@ from migen import * -from litex_boards.platforms import arty +from litex_boards.platforms import digilent_arty from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -71,7 +71,7 @@ class BaseSoC(SoCCore): with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_jtagbone=True, with_spi_flash=False, with_pmod_gpio=False, **kwargs): - platform = arty.Platform(variant=variant, toolchain=toolchain) + platform = digilent_arty.Platform(variant=variant, toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0) @@ -120,7 +120,7 @@ class BaseSoC(SoCCore): # GPIOs ------------------------------------------------------------------------------------ if with_pmod_gpio: - platform.add_extension(arty.raw_pmod_io("pmoda")) + platform.add_extension(digilent_arty.raw_pmod_io("pmoda")) self.submodules.gpio = GPIOTristate(platform.request("pmoda")) # Build -------------------------------------------------------------------------------------------- @@ -168,9 +168,9 @@ def main(): **soc_core_argdict(args) ) if args.sdcard_adapter == "numato": - soc.platform.add_extension(arty._numato_sdcard_pmod_io) + soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io) else: - soc.platform.add_extension(arty._sdcard_pmod_io) + soc.platform.add_extension(digilent_arty._sdcard_pmod_io) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: diff --git a/litex_boards/targets/digilent_arty_s7.py b/litex_boards/targets/digilent_arty_s7.py index d86cc7f..4093f42 100755 --- a/litex_boards/targets/digilent_arty_s7.py +++ b/litex_boards/targets/digilent_arty_s7.py @@ -9,7 +9,7 @@ from migen import * -from litex_boards.platforms import arty_s7 +from litex_boards.platforms import digilent_arty_s7 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -49,7 +49,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs): - platform = arty_s7.Platform(variant=variant) + platform = digilent_arty_s7.Platform(variant=variant) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/digilent_atlys.py b/litex_boards/targets/digilent_atlys.py index 09ed48c..858430f 100755 --- a/litex_boards/targets/digilent_atlys.py +++ b/litex_boards/targets/digilent_atlys.py @@ -15,7 +15,7 @@ from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import atlys +from litex_boards.platforms import digilent_atlys from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * @@ -149,7 +149,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, with_ethernet=True, with_etherbone=False, eth_phy=0, **kwargs): sys_clk_freq = int(75e6) - platform = atlys.Platform() + platform = digilent_atlys.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/digilent_basys3.py b/litex_boards/targets/digilent_basys3.py index af2c49d..eb831bd 100755 --- a/litex_boards/targets/digilent_basys3.py +++ b/litex_boards/targets/digilent_basys3.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import basys3 +from litex_boards.platforms import digilent_basys3 from litex.soc.cores.clock import * from litex.soc.integration.soc import SoCRegion @@ -38,7 +38,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_video_terminal=False, **kwargs): - platform = basys3.Platform() + platform = digilent_basys3.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -81,7 +81,7 @@ def main(): with_video_terminal = args.with_video_terminal, **soc_core_argdict(args) ) - soc.platform.add_extension(basys3._sdcard_pmod_io) + soc.platform.add_extension(digilent_basys3._sdcard_pmod_io) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: diff --git a/litex_boards/targets/digilent_genesys2.py b/litex_boards/targets/digilent_genesys2.py index 0d63672..d6f2a58 100755 --- a/litex_boards/targets/digilent_genesys2.py +++ b/litex_boards/targets/digilent_genesys2.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import genesys2 +from litex_boards.platforms import digilent_genesys2 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -46,7 +46,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, with_led_chaser=True, **kwargs): - platform = genesys2.Platform() + platform = digilent_genesys2.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/digilent_nexys4ddr.py b/litex_boards/targets/digilent_nexys4ddr.py index bf95bff..83be46b 100755 --- a/litex_boards/targets/digilent_nexys4ddr.py +++ b/litex_boards/targets/digilent_nexys4ddr.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import nexys4ddr +from litex_boards.platforms import digilent_nexys4ddr from litex.soc.cores.clock import * from litex.soc.integration.soc import SoCRegion @@ -54,7 +54,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs): - platform = nexys4ddr.Platform() + platform = digilent_nexys4ddr.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/digilent_nexys_video.py b/litex_boards/targets/digilent_nexys_video.py index 244b7b3..4196def 100755 --- a/litex_boards/targets/digilent_nexys_video.py +++ b/litex_boards/targets/digilent_nexys_video.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import nexys_video +from litex_boards.platforms import digilent_nexys_video from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -77,7 +77,7 @@ class BaseSoC(SoCCore): def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_led_chaser=True, with_sata=False, sata_gen="gen2", with_sata_pll_refclk=False, vadj="1.2V", with_video_terminal=False, with_video_framebuffer=False, **kwargs): - platform = nexys_video.Platform(toolchain=toolchain) + platform = digilent_nexys_video.Platform(toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- with_video_pll = (with_video_terminal or with_video_framebuffer) diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py index 7a5ee2f..0ef24b6 100755 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import pynq_z1 +from litex_boards.platforms import digilent_pynq_z1 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.interconnect import axi @@ -59,7 +59,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs): - platform = pynq_z1.Platform() + platform = digilent_pynq_z1.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal) diff --git a/litex_boards/targets/enclustra_mercury_kx2.py b/litex_boards/targets/enclustra_mercury_kx2.py index 1e4fbe8..773dd6a 100755 --- a/litex_boards/targets/enclustra_mercury_kx2.py +++ b/litex_boards/targets/enclustra_mercury_kx2.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import mercury_kx2 +from litex_boards.platforms import enclustra_mercury_kx2 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -44,7 +44,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): - platform = mercury_kx2.Platform() + platform = enclustra_mercury_kx2.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/enclustra_mercury_xu5.py b/litex_boards/targets/enclustra_mercury_xu5.py index 9465dd5..7642a36 100755 --- a/litex_boards/targets/enclustra_mercury_xu5.py +++ b/litex_boards/targets/enclustra_mercury_xu5.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import mercury_xu5 +from litex_boards.platforms import enclustra_mercury_xu5 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -52,7 +52,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): - platform = mercury_xu5.Platform() + platform = enclustra_mercury_xu5.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index 44ad23f..f29218b 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -15,7 +15,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import butterstick +from litex_boards.platforms import gsd_butterstick from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): with_led_chaser = True, with_syzygy_gpio = True, **kwargs) : - platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain) + platform = gsd_butterstick.Platform(revision=revision, device=device ,toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -145,7 +145,7 @@ class BaseSoC(SoCCore): # GPIOs ------------------------------------------------------------------------------------ if with_syzygy_gpio: - platform.add_extension(butterstick.raw_syzygy_io("SYZYGY0")) + platform.add_extension(gsd_butterstick.raw_syzygy_io("SYZYGY0")) self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0")) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py index 3cbbc72..e427040 100755 --- a/litex_boards/targets/gsd_orangecrab.py +++ b/litex_boards/targets/gsd_orangecrab.py @@ -13,7 +13,7 @@ from migen import * from migen.genlib.misc import WaitTimer from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import orangecrab +from litex_boards.platforms import gsd_orangecrab from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -146,7 +146,7 @@ class _CRGSDRAM(Module): class BaseSoC(SoCCore): def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16", sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs): - platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) + platform = gsd_orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- crg_cls = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG diff --git a/litex_boards/targets/hackaday_hadbadge.py b/litex_boards/targets/hackaday_hadbadge.py index d916b78..dfb2d9e 100755 --- a/litex_boards/targets/hackaday_hadbadge.py +++ b/litex_boards/targets/hackaday_hadbadge.py @@ -14,7 +14,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import hadbadge +from litex_boards.platforms import hackaday_hadbadge from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -54,7 +54,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs): - platform = hadbadge.Platform(toolchain=toolchain) + platform = hackaday_hadbadge.Platform(toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py index 1e56c43..a731a52 100755 --- a/litex_boards/targets/kosagi_fomu.py +++ b/litex_boards/targets/kosagi_fomu.py @@ -14,7 +14,7 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import fomu_pvt +from litex_boards.platforms import kosagi_fomu_pvt from litex.soc.cores.ram import Up5kSPRAM from litex.soc.cores.clock import iCE40PLL @@ -69,7 +69,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs): - platform = fomu_pvt.Platform() + platform = kosagi_fomu_pvt.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/kosagi_netv2.py b/litex_boards/targets/kosagi_netv2.py index dd5558a..0340b00 100755 --- a/litex_boards/targets/kosagi_netv2.py +++ b/litex_boards/targets/kosagi_netv2.py @@ -10,7 +10,7 @@ import os from migen import * -from litex_boards.platforms import netv2 +from litex_boards.platforms import kosagi_netv2 from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * @@ -61,7 +61,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, with_led_chaser=True, **kwargs): - platform = netv2.Platform(variant=variant) + platform = kosagi_netv2.Platform(variant=variant) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index 9745627..f9063c3 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -11,7 +11,7 @@ import os from migen import * -from litex_boards.platforms import snickerdoodle +from litex_boards.platforms import krtkl_snickerdoodle from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.interconnect import axi @@ -25,7 +25,7 @@ from litex.soc.cores.led import LedChaser # UTILS --------------------------------------------------------------------------------------------- def load_ps7(soc, xci_file): - odir = os.path.join("build", "snickerdoodle", "gateware", "xci") + odir = os.path.join("build", "krtkl_snickerdoodle", "gateware", "xci") os.makedirs(odir, exist_ok=True) file = "snickerdoodle_ps7.xci" dst = os.path.join(odir, file) @@ -67,7 +67,7 @@ class BaseSoC(SoCCore): xci_file = None, **kwargs): - platform = snickerdoodle.Platform(variant=variant) + platform = krtkl_snickerdoodle.Platform(variant=variant) # CRG -------------------------------------------------------------------------------------- if ext_clk_freq: diff --git a/litex_boards/targets/lambdaconcept_ecpix5.py b/litex_boards/targets/lambdaconcept_ecpix5.py index 0b5e21c..1fbb2e7 100755 --- a/litex_boards/targets/lambdaconcept_ecpix5.py +++ b/litex_boards/targets/lambdaconcept_ecpix5.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import ecpix5 +from litex_boards.platforms import lambdaconcept_ecpix5 from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -82,7 +82,7 @@ class BaseSoC(SoCCore): with_video_framebuffer = False, with_led_chaser = True, **kwargs): - platform = ecpix5.Platform(device=device, toolchain="trellis") + platform = lambdaconcept_ecpix5.Platform(device=device, toolchain="trellis") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index b5c3cde..eb1688e 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import crosslink_nx_evn +from litex_boards.platforms import lattice_crosslink_nx_evn from litex.soc.cores.ram import NXLRAM from litex.soc.cores.clock import NXPLL @@ -65,7 +65,7 @@ class BaseSoC(SoCCore): "csr" : 0xf0000000, } def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG400C", toolchain="radiant", with_led_chaser=True, **kwargs): - platform = crosslink_nx_evn.Platform(device=device, toolchain=toolchain) + platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -74,7 +74,7 @@ class BaseSoC(SoCCore): # Disable Integrated SRAM since we want to instantiate LRAM specifically for it kwargs["integrated_sram_size"] = 0 # Make serial_pmods available - platform.add_extension(crosslink_nx_evn.serial_pmods) + platform.add_extension(lattice_crosslink_nx_evn.serial_pmods) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs) # 128KB LRAM (used as SRAM) --------------------------------------------------------------- diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index c55c2b9..a35e315 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -12,9 +12,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import crosslink_nx_vip - -from litex_boards.platforms import crosslink_nx_vip +from litex_boards.platforms import lattice_crosslink_nx_vip from litex.soc.cores.hyperbus import HyperRAM @@ -68,7 +66,7 @@ class BaseSoC(SoCCore): } def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", with_led_chaser=True, **kwargs): - platform = crosslink_nx_vip.Platform(toolchain=toolchain) + platform = lattice_crosslink_nx_vip.Platform(toolchain=toolchain) platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") # CRG -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/lattice_ecp5_evn.py b/litex_boards/targets/lattice_ecp5_evn.py index 30d280d..a3dcff3 100755 --- a/litex_boards/targets/lattice_ecp5_evn.py +++ b/litex_boards/targets/lattice_ecp5_evn.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import ecp5_evn +from litex_boards.platforms import lattice_ecp5_evn from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -44,7 +44,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", with_led_chaser=True, **kwargs): - platform = ecp5_evn.Platform(toolchain=toolchain) + platform = lattice_ecp5_evn.Platform(toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, x5_clk_freq) diff --git a/litex_boards/targets/lattice_ecp5_vip.py b/litex_boards/targets/lattice_ecp5_vip.py index e4d4e4c..5d50dfe 100755 --- a/litex_boards/targets/lattice_ecp5_vip.py +++ b/litex_boards/targets/lattice_ecp5_vip.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import ecp5_vip +from litex_boards.platforms import lattice_ecp5_vip from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -86,7 +86,7 @@ class BaseSoC(SoCCore): with_video_terminal = True, with_video_framebuffer = False, **kwargs): - platform = ecp5_vip.Platform(toolchain=toolchain) + platform = lattice_ecp5_vip.Platform(toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/lattice_versa_ecp5.py b/litex_boards/targets/lattice_versa_ecp5.py index 75e0a72..c7ce25d 100755 --- a/litex_boards/targets/lattice_versa_ecp5.py +++ b/litex_boards/targets/lattice_versa_ecp5.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import versa_ecp5 +from litex_boards.platforms import lattice_versa_ecp5 from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -77,7 +77,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_led_chaser=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs): - platform = versa_ecp5.Platform(toolchain=toolchain, device=device) + platform = lattice_versa_ecp5.Platform(toolchain=toolchain, device=device) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/myminieye_runber.py b/litex_boards/targets/myminieye_runber.py index 81cdaa6..62d629b 100755 --- a/litex_boards/targets/myminieye_runber.py +++ b/litex_boards/targets/myminieye_runber.py @@ -13,7 +13,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litex_boards.platforms import runber +from litex_boards.platforms import myminieye_runber # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -33,7 +33,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs): - platform = runber.Platform() + platform = myminieye_runber.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/numato_aller.py b/litex_boards/targets/numato_aller.py index 9dcc5ba..508a1ed 100755 --- a/litex_boards/targets/numato_aller.py +++ b/litex_boards/targets/numato_aller.py @@ -11,7 +11,7 @@ import os from migen import * -from litex_boards.platforms import aller +from litex_boards.platforms import numato_aller from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * @@ -55,7 +55,7 @@ class CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs): - platform = aller.Platform() + platform = numato_aller.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/numato_mimas_a7.py b/litex_boards/targets/numato_mimas_a7.py index 7b53bb9..2fc76dc 100755 --- a/litex_boards/targets/numato_mimas_a7.py +++ b/litex_boards/targets/numato_mimas_a7.py @@ -9,7 +9,7 @@ from migen import * -from litex_boards.platforms import mimas_a7 +from litex_boards.platforms import numato_mimas_a7 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -50,7 +50,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_ethernet=False, **kwargs): - platform = mimas_a7.Platform() + platform = numato_mimas_a7.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/numato_nereid.py b/litex_boards/targets/numato_nereid.py index 6a6f5d0..66a73d8 100755 --- a/litex_boards/targets/numato_nereid.py +++ b/litex_boards/targets/numato_nereid.py @@ -11,7 +11,7 @@ import os from migen import * -from litex_boards.platforms import nereid +from litex_boards.platforms import numato_nereid from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * @@ -52,7 +52,7 @@ class CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): - platform = nereid.Platform() + platform = numato_nereid.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/numato_tagus.py b/litex_boards/targets/numato_tagus.py index b3db7f5..c4bcd18 100755 --- a/litex_boards/targets/numato_tagus.py +++ b/litex_boards/targets/numato_tagus.py @@ -11,7 +11,7 @@ import os from migen import * -from litex_boards.platforms import tagus +from litex_boards.platforms import numato_tagus from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * @@ -56,7 +56,7 @@ class CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs): - platform = tagus.Platform() + platform = numato_tagus.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py index 449b9d9..dea2d71 100755 --- a/litex_boards/targets/qwertyembedded_beaglewire.py +++ b/litex_boards/targets/qwertyembedded_beaglewire.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import beaglewire +from litex_boards.platforms import qwertyembedded_beaglewire from litex.build.io import DDROutput @@ -64,7 +64,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, bios_flash_offset, sys_clk_freq=int(50e6), **kwargs): - platform = beaglewire.Platform() + platform = qwertyembedded_beaglewire.Platform() # Disable Integrated ROM since too large for iCE40. kwargs["integrated_rom_size"] = 0 diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py index 1eb300d..f891b18 100755 --- a/litex_boards/targets/radiona_ulx3s.py +++ b/litex_boards/targets/radiona_ulx3s.py @@ -12,7 +12,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import ulx3s +from litex_boards.platforms import radiona_ulx3s from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -90,7 +90,7 @@ class BaseSoC(SoCCore): sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_spi_flash=False, **kwargs): - platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain) + platform = radiona_ulx3s.Platform(device=device, revision=revision, toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" diff --git a/litex_boards/targets/rz_easyfpga.py b/litex_boards/targets/rz_easyfpga.py index e0dee0c..386e3ca 100755 --- a/litex_boards/targets/rz_easyfpga.py +++ b/litex_boards/targets/rz_easyfpga.py @@ -10,7 +10,7 @@ from migen import * from litex.build.io import DDROutput -from litex_boards.platforms import easyfpga +from litex_boards.platforms import rz_easyfpga from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * @@ -56,7 +56,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, sdram_rate="1:1", **kwargs): - platform = easyfpga.Platform() + platform = rz_easyfpga.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) diff --git a/litex_boards/targets/saanlima_pipistrello.py b/litex_boards/targets/saanlima_pipistrello.py index 38172e4..53fbbf1 100755 --- a/litex_boards/targets/saanlima_pipistrello.py +++ b/litex_boards/targets/saanlima_pipistrello.py @@ -15,7 +15,7 @@ from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import pipistrello +from litex_boards.platforms import saanlima_pipistrello from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * @@ -153,7 +153,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, with_led_chaser=True, **kwargs): sys_clk_freq = (83 + Fraction(1, 3))*1000*1000 - platform = pipistrello.Platform() + platform = saanlima_pipistrello.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/scarabhardware_minispartan6.py b/litex_boards/targets/scarabhardware_minispartan6.py index c48dc7f..4a29ee3 100755 --- a/litex_boards/targets/scarabhardware_minispartan6.py +++ b/litex_boards/targets/scarabhardware_minispartan6.py @@ -13,7 +13,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import minispartan6 +from litex_boards.platforms import scarabhardware_minispartan6 from litex.soc.cores.clock import S6PLL from litex.soc.integration.soc_core import * @@ -66,7 +66,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs): - platform = minispartan6.Platform() + platform = scarabhardware_minispartan6.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) diff --git a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py index 1b23757..f3e36c0 100755 --- a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py +++ b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py @@ -11,7 +11,7 @@ from migen import * from litex.build.generic_platform import * from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict -from litex_boards.platforms import spartan_edge_accelerator +from litex_boards.platforms import seeedstudio_spartan_edge_accelerator from litex.soc.cores.clock import * from litex.soc.integration.soc import SoCRegion @@ -67,7 +67,7 @@ class BaseSoC(SoCCore): with_video_terminal = True, with_neopixel = False, **kwargs): - platform = spartan_edge_accelerator.Platform() + platform = seeedstudio_spartan_edge_accelerator.Platform() platform.add_extension(_serial_io) # CRG -------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index be2ee0b..8daac0d 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -20,7 +20,7 @@ from migen import * -from litex_boards.platforms import sds1104xe +from litex_boards.platforms import siglent_sds1104xe from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * @@ -66,7 +66,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs): - platform = sds1104xe.Platform() + platform = siglent_sds1104xe.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone) diff --git a/litex_boards/targets/sipeed_tang_nano.py b/litex_boards/targets/sipeed_tang_nano.py index c050258..1120d93 100755 --- a/litex_boards/targets/sipeed_tang_nano.py +++ b/litex_boards/targets/sipeed_tang_nano.py @@ -30,15 +30,14 @@ # 5) Test UARTBone ex: litex_cli --regs from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex_boards.platforms import sipeed_tang_nano from litex.soc.cores.clock.gowin_gw1n import GW1NPLL from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litex_boards.platforms import tang_nano - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -62,7 +61,7 @@ class _CRG(Module): class BaseSoC(SoCMini): def __init__(self, sys_clk_freq=int(48e6), with_led_chaser=True, **kwargs): - platform = tang_nano.Platform() + platform = sipeed_tang_nano.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index e8f713d..9387c24 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -7,7 +7,8 @@ # SPDX-License-Identifier: BSD-2-Clause from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex_boards.platforms import sipeed_tang_nano_4k from litex.soc.cores.clock.gowin_gw1n import GW1NPLL from litex.soc.integration.soc_core import * @@ -16,8 +17,6 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.video import * -from litex_boards.platforms import tang_nano_4k - from litex.soc.cores.hyperbus import HyperRAM kB = 1024 @@ -62,7 +61,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs): - platform = tang_nano_4k.Platform() + platform = sipeed_tang_nano_4k.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal) diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py index 6cbccd2..ac52005 100755 --- a/litex_boards/targets/sipeed_tang_nano_9k.py +++ b/litex_boards/targets/sipeed_tang_nano_9k.py @@ -7,7 +7,8 @@ # SPDX-License-Identifier: BSD-2-Clause from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex_boards.platforms import tang_nano_9k from litex.soc.cores.clock.gowin_gw1n import GW1NPLL from litex.soc.integration.soc_core import * @@ -16,8 +17,6 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.video import * -from litex_boards.platforms import tang_nano_9k - from litex.soc.cores.hyperbus import HyperRAM kB = 1024 diff --git a/litex_boards/targets/sipeed_tang_primer.py b/litex_boards/targets/sipeed_tang_primer.py index 2d808bb..cc844bd 100755 --- a/litex_boards/targets/sipeed_tang_primer.py +++ b/litex_boards/targets/sipeed_tang_primer.py @@ -69,7 +69,7 @@ def main(): args = parser.parse_args() soc = BaseSoC( - sys_clk_freq = int(float(args.sys_clk_freq)), + sys_clk_freq = int(float(args.sys_clk_freq)), **soc_core_argdict(args) ) diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py index 50e1d31..8dc22e9 100755 --- a/litex_boards/targets/sqrl_acorn.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -27,7 +27,7 @@ import os from migen import * -from litex_boards.platforms import acorn +from litex_boards.platforms import sqrl_acorn from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * @@ -74,7 +74,7 @@ class CRG(Module): class BaseSoC(SoCCore): def __init__(self, variant="cle-215+", sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): - platform = acorn.Platform(variant=variant) + platform = sqrl_acorn.Platform(variant=variant) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) @@ -104,7 +104,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) diff --git a/litex_boards/targets/sqrl_fk33.py b/litex_boards/targets/sqrl_fk33.py index a4934eb..f87e2d5 100755 --- a/litex_boards/targets/sqrl_fk33.py +++ b/litex_boards/targets/sqrl_fk33.py @@ -15,7 +15,7 @@ import os from migen import * -from litex_boards.platforms import fk33 +from litex_boards.platforms import sqrl_fk33 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -57,7 +57,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, with_hbm=False, **kwargs): - platform = fk33.Platform() + platform = sqrl_fk33.Platform() if with_hbm: assert 225e6 <= sys_clk_freq <= 450e6 diff --git a/litex_boards/targets/sqrl_xcu1525.py b/litex_boards/targets/sqrl_xcu1525.py index a4569c5..9cac80e 100755 --- a/litex_boards/targets/sqrl_xcu1525.py +++ b/litex_boards/targets/sqrl_xcu1525.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import xcu1525 +from litex_boards.platforms import sqrl_xcu1525 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -58,7 +58,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): - platform = xcu1525.Platform() + platform = sqrl_xcu1525.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel) diff --git a/litex_boards/targets/terasic_de0nano.py b/litex_boards/targets/terasic_de0nano.py index 765c16b..bf13834 100755 --- a/litex_boards/targets/terasic_de0nano.py +++ b/litex_boards/targets/terasic_de0nano.py @@ -15,7 +15,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import de0nano +from litex_boards.platforms import terasic_de0nano from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * @@ -61,7 +61,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", with_led_chaser=True, **kwargs): - platform = de0nano.Platform() + platform = terasic_de0nano.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) diff --git a/litex_boards/targets/terasic_de10lite.py b/litex_boards/targets/terasic_de10lite.py index 14d392f..a21b20d 100755 --- a/litex_boards/targets/terasic_de10lite.py +++ b/litex_boards/targets/terasic_de10lite.py @@ -11,7 +11,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import de10lite +from litex_boards.platforms import terasic_de10lite from litex.soc.cores.clock import Max10PLL from litex.soc.integration.soc import SoCRegion @@ -53,7 +53,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False, **kwargs): - platform = de10lite.Platform() + platform = terasic_de10lite.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/terasic_de10nano.py b/litex_boards/targets/terasic_de10nano.py index fff6236..029b72b 100755 --- a/litex_boards/targets/terasic_de10nano.py +++ b/litex_boards/targets/terasic_de10nano.py @@ -11,7 +11,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import de10nano +from litex_boards.platforms import terasic_de10nano from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.soc import SoCRegion @@ -63,7 +63,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_mister_sdram=True, with_mister_video_terminal=False, sdram_rate="1:1", **kwargs): - platform = de10nano.Platform() + platform = terasic_de10nano.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram, sdram_rate=sdram_rate) diff --git a/litex_boards/targets/terasic_de1soc.py b/litex_boards/targets/terasic_de1soc.py index c1fb757..1f01598 100755 --- a/litex_boards/targets/terasic_de1soc.py +++ b/litex_boards/targets/terasic_de1soc.py @@ -11,7 +11,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import de1soc +from litex_boards.platforms import terasic_de1soc from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.soc_core import * @@ -48,7 +48,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs): - platform = de1soc.Platform() + platform = terasic_de1soc.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/terasic_de2_115.py b/litex_boards/targets/terasic_de2_115.py index 10282d3..fbeae89 100755 --- a/litex_boards/targets/terasic_de2_115.py +++ b/litex_boards/targets/terasic_de2_115.py @@ -11,7 +11,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput -from litex_boards.platforms import de2_115 +from litex_boards.platforms import terasic_de2_115 from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * @@ -47,7 +47,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): - platform = de2_115.Platform() + platform = terasic_de2_115.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py index f7d6389..22416d4 100755 --- a/litex_boards/targets/terasic_deca.py +++ b/litex_boards/targets/terasic_deca.py @@ -11,7 +11,7 @@ # litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag from migen import * -from litex_boards.platforms import deca +from litex_boards.platforms import terasic_deca from litex.soc.cores.clock import Max10PLL from litex.soc.integration.soc_core import * @@ -58,7 +58,7 @@ class BaseSoC(SoCCore): with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, **kwargs): - self.platform = platform = deca.Platform() + self.platform = platform = terasic_deca.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False) diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index 908894a..69ee2b6 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -10,7 +10,7 @@ from migen import * -from litex_boards.platforms import c10lprefkit +from litex_boards.platforms import trenz_c10lprefkit from litex.soc.cores.clock import Cyclone10LPPLL from litex.soc.integration.soc_core import * @@ -58,7 +58,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_ethernet=False, with_etherbone=False, **kwargs): - platform = c10lprefkit.Platform() + platform = trenz_c10lprefkit.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/trenz_cyc1000.py b/litex_boards/targets/trenz_cyc1000.py index 61cefaf..a48ad7e 100755 --- a/litex_boards/targets/trenz_cyc1000.py +++ b/litex_boards/targets/trenz_cyc1000.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import cyc1000 +from litex_boards.platforms import trenz_cyc1000 from litex.soc.cores.clock import Cyclone10LPPLL from litex.soc.integration.soc_core import * @@ -45,7 +45,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs): - platform = cyc1000.Platform() + platform = trenz_cyc1000.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/trenz_max1000.py b/litex_boards/targets/trenz_max1000.py index f9b930d..4e28272 100755 --- a/litex_boards/targets/trenz_max1000.py +++ b/litex_boards/targets/trenz_max1000.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import max1000 +from litex_boards.platforms import trenz_max1000 from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.soc_core import * @@ -45,7 +45,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs): - platform = max1000.Platform() + platform = trenz_max1000.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index 176923e..9998dd1 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -10,6 +10,8 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex_boards.platforms import trenz_tec0117 + from litex.build.io import DDROutput from litex.soc.cores.clock.gowin_gw1n import GW1NPLL @@ -18,8 +20,6 @@ from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litex_boards.platforms import tec0117 - from litedram.modules import MT48LC4M16 # FIXME: use EtronTech reference. from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY @@ -58,7 +58,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1", with_led_chaser=True, **kwargs): - platform = tec0117.Platform() + platform = trenz_tec0117.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -119,7 +119,7 @@ class BaseSoC(SoCCore): def flash(bios_flash_offset): # Create FTDI <--> SPI Flash proxy bitstream and load it. # ------------------------------------------------------- - platform = tec0117.Platform() + platform = trenz_tec0117.Platform() flash = platform.request("spiflash", 0) bus = platform.request("spiflash", 1) module = Module() @@ -168,7 +168,7 @@ def main(): sys_clk_freq = int(float(args.sys_clk_freq)), **soc_core_argdict(args) ) - soc.platform.add_extension(tec0117._sdcard_pmod_io) + soc.platform.add_extension(trenz_tec0117._sdcard_pmod_io) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: diff --git a/litex_boards/targets/tul_pynq_z2.py b/litex_boards/targets/tul_pynq_z2.py index 82bbb9f..90357f0 100755 --- a/litex_boards/targets/tul_pynq_z2.py +++ b/litex_boards/targets/tul_pynq_z2.py @@ -9,7 +9,7 @@ from migen import * -from litex_boards.platforms import pynq_z2 +from litex_boards.platforms import tul_pynq_z2 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.interconnect import axi @@ -44,7 +44,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): - platform = pynq_z2.Platform() + platform = tul_pynq_z2.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_ac701.py b/litex_boards/targets/xilinx_ac701.py index 612de54..027f1c8 100755 --- a/litex_boards/targets/xilinx_ac701.py +++ b/litex_boards/targets/xilinx_ac701.py @@ -11,7 +11,7 @@ import os from migen import * -from litex_boards.platforms import ac701 +from litex_boards.platforms import xilinx_ac701 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -57,7 +57,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, eth_phy="rgmii", with_spi_flash=False, with_led_chaser=True, with_pcie=False, **kwargs): - platform = ac701.Platform() + platform = xilinx_ac701.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py index 3399292..ff23d95 100755 --- a/litex_boards/targets/xilinx_alveo_u250.py +++ b/litex_boards/targets/xilinx_alveo_u250.py @@ -13,7 +13,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import alveo_u250 +from litex_boards.platforms import xilinx_alveo_u250 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -59,7 +59,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs): - platform = alveo_u250.Platform() + platform = xilinx_alveo_u250.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index 42437df..13a827e 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -17,7 +17,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import alveo_u280 +from litex_boards.platforms import xilinx_alveo_u280 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -86,7 +86,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led_chaser=False, with_hbm=False, **kwargs): - platform = alveo_u280.Platform() + platform = xilinx_alveo_u280.Platform() if with_hbm: assert 225e6 <= sys_clk_freq <= 450e6 diff --git a/litex_boards/targets/xilinx_kc705.py b/litex_boards/targets/xilinx_kc705.py index ff9f68f..08d2a7d 100755 --- a/litex_boards/targets/xilinx_kc705.py +++ b/litex_boards/targets/xilinx_kc705.py @@ -12,7 +12,7 @@ import os from migen import * -from litex_boards.platforms import kc705 +from litex_boards.platforms import xilinx_kc705 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -53,7 +53,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_led_chaser=True, with_spi_flash=False, with_pcie=False, with_sata=False, **kwargs): - platform = kc705.Platform() + platform = xilinx_kc705.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_kcu105.py b/litex_boards/targets/xilinx_kcu105.py index 5f38bda..1167f5b 100755 --- a/litex_boards/targets/xilinx_kcu105.py +++ b/litex_boards/targets/xilinx_kcu105.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import kcu105 +from litex_boards.platforms import xilinx_kcu105 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -63,7 +63,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): - platform = kcu105.Platform() + platform = xilinx_kcu105.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_vc707.py b/litex_boards/targets/xilinx_vc707.py index 9381190..e4cc35a 100755 --- a/litex_boards/targets/xilinx_vc707.py +++ b/litex_boards/targets/xilinx_vc707.py @@ -9,7 +9,7 @@ import os from migen import * -from litex_boards.platforms import vc707 +from litex_boards.platforms import xilinx_vc707 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -48,7 +48,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs): - platform = vc707.Platform() + platform = xilinx_vc707.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_vcu118.py b/litex_boards/targets/xilinx_vcu118.py index 45a5f50..d177ff6 100755 --- a/litex_boards/targets/xilinx_vcu118.py +++ b/litex_boards/targets/xilinx_vcu118.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import vcu118 +from litex_boards.platforms import xilinx_vcu118 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -53,7 +53,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): - platform = vcu118.Platform() + platform = xilinx_vcu118.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_zcu102.py b/litex_boards/targets/xilinx_zcu102.py index 1666b44..3bd9837 100755 --- a/litex_boards/targets/xilinx_zcu102.py +++ b/litex_boards/targets/xilinx_zcu102.py @@ -8,7 +8,7 @@ from migen import * -from litex_boards.platforms import zcu102 +from litex_boards.platforms import xilinx_zcu102 from litex.build.io import CRG @@ -22,7 +22,7 @@ from litex.soc.cores.led import LedChaser class BaseSoC(SoCCore): def __init__(self, sys_clk_freq, with_ethernet=False, with_led_chaser=True, **kwargs): - platform = zcu102.Platform() + platform = xilinx_zcu102.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(sys_clk_freq) diff --git a/litex_boards/targets/xilinx_zcu104.py b/litex_boards/targets/xilinx_zcu104.py index b3e2f26..38fbf98 100755 --- a/litex_boards/targets/xilinx_zcu104.py +++ b/litex_boards/targets/xilinx_zcu104.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import zcu104 +from litex_boards.platforms import xilinx_zcu104 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -54,7 +54,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): - platform = zcu104.Platform() + platform = xilinx_zcu104.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/xilinx_zcu106.py b/litex_boards/targets/xilinx_zcu106.py index abdfcee..4060f2f 100755 --- a/litex_boards/targets/xilinx_zcu106.py +++ b/litex_boards/targets/xilinx_zcu106.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import zcu106 +from litex_boards.platforms import xilinx_zcu106 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -58,7 +58,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs): - platform = zcu106.Platform() + platform = xilinx_zcu106.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU106", **kwargs) diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index bc934fd..ef860a9 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -9,6 +9,7 @@ from migen import * from litex_boards.platforms import xilinx_zcu216 + from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.build.tools import write_to_file diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index 1fcfd55..2e7a9fd 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -8,7 +8,8 @@ from migen import * -from litex_boards.platforms import zybo_z7 +from litex_boards.platforms import digilent_zybo_z7 + from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.interconnect import axi @@ -43,7 +44,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs): - platform = zybo_z7.Platform() + platform = digilent_zybo_z7.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq)