From 87df45e625ee15e558f34f4a7319c54d02ce4fe4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 26 Mar 2021 23:25:42 +0100
Subject: [PATCH] siglent_sds1104xe: Allow build without Etherbone.
---
litex_boards/targets/siglent_sds1104xe.py | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py
index 80c7e1d..78ba166 100755
--- a/litex_boards/targets/siglent_sds1104xe.py
+++ b/litex_boards/targets/siglent_sds1104xe.py
@@ -39,7 +39,7 @@ from liteeth.phy.mii import LiteEthPHYMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
- def __init__(self, platform, sys_clk_freq):
+ def __init__(self, platform, sys_clk_freq, with_ethernet=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@@ -49,8 +49,12 @@ class _CRG(Module):
# # #
+ # Clk / Rst
+ clk25 = ClockSignal("eth_tx") if with_ethernet else platform.request("eth_clocks").rx
+
+ # PLL
self.submodules.pll = pll = S7PLL(speedgrade=-1)
- pll.register_clkin(ClockSignal("eth_tx"), 25e6)
+ pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
@@ -75,7 +79,7 @@ class BaseSoC(SoCCore):
**kwargs)
# CRG --------------------------------------------------------------------------------------
- self.submodules.crg = _CRG(platform, sys_clk_freq)
+ self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: