diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index 68be67b..4d0bb9d 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
 
         # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
         self.spram = Up5kSPRAM(size=128 * KILOBYTE)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
 
         # SPI Flash --------------------------------------------------------------------------------
         # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA
diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py
index e532222..b030d59 100755
--- a/litex_boards/targets/muselab_icesugar.py
+++ b/litex_boards/targets/muselab_icesugar.py
@@ -73,7 +73,7 @@ class BaseSoC(SoCCore):
 
         # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
         self.spram = Up5kSPRAM(size=64 * KILOBYTE)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * KILOBYTE))
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=64 * KILOBYTE))
 
         # SPI Flash --------------------------------------------------------------------------------
         from litespi.modules import W25Q64FV