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targets: Map SPRAM to SRAM when use as SRAM.

This commit is contained in:
Florent Kermarrec 2024-07-17 11:01:34 +02:00
parent 524387b45d
commit 88ab3eca6f
2 changed files with 2 additions and 2 deletions
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2
litex_boards/targets/lattice_ice40up5k_evn.py
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@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as SRAM) --------------------------------------------------------------- # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.spram = Up5kSPRAM(size=128 * KILOBYTE) self.spram = Up5kSPRAM(size=128 * KILOBYTE)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * KILOBYTE)) self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
# SPI Flash -------------------------------------------------------------------------------- # SPI Flash --------------------------------------------------------------------------------
# 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA

2
litex_boards/targets/muselab_icesugar.py
View File

@ -73,7 +73,7 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as SRAM) --------------------------------------------------------------- # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.spram = Up5kSPRAM(size=64 * KILOBYTE) self.spram = Up5kSPRAM(size=64 * KILOBYTE)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * KILOBYTE)) self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=64 * KILOBYTE))
# SPI Flash -------------------------------------------------------------------------------- # SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q64FV from litespi.modules import W25Q64FV