diff --git a/litex_boards/platforms/orangecrab.py b/litex_boards/platforms/orangecrab.py
index f2c6b09..913988e 100644
--- a/litex_boards/platforms/orangecrab.py
+++ b/litex_boards/platforms/orangecrab.py
@@ -1,4 +1,4 @@
-# This file is Copyright (c) 2019 Greg Davill <greg.davill@gmail.com>
+# This file is Copyright (c) Greg Davill <greg.davill@gmail.com>
 # License: BSD
 
 from litex.build.generic_platform import *
@@ -10,16 +10,11 @@ _io = [
     ("clk48", 0,  Pins("A9"),  IOStandard("LVCMOS33")),
 
     ("rgb_led", 0,
-        Subsignal("r", Pins("V17"), IOStandard("LVCMOS25")),
-        Subsignal("g", Pins("T17"), IOStandard("LVCMOS25")),
+        Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")),
+        Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")),
         Subsignal("b", Pins("J3"),  IOStandard("LVCMOS33")),
     ),
 
-    ("serial", 0,
-        Subsignal("tx", Pins("N17"), IOStandard("LVCMOS25")),
-        Subsignal("rx", Pins("M18"), IOStandard("LVCMOS25")),
-    ),
-
     ("ddram", 0,
         Subsignal("a", Pins(
             "A4 D2 C3 C7 D3 D4 D1 B2",
@@ -48,15 +43,55 @@ _io = [
         Subsignal("cs_n", Pins("U17")),
         Subsignal("clk", Pins("U16")),
         Subsignal("dq", Pins("U18", "T18", "R18", "N18")),
-        IOStandard("LVCMOS25")
+        IOStandard("LVCMOS33")
+    ),
+
+    ("spi-internal", 0,
+        Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")),
+        Subsignal("clk",  Pins("C11")),
+        Subsignal("miso",   Pins("A11"), Misc("PULLMODE=UP")),
+        Subsignal("mosi",   Pins("A10"), Misc("PULLMODE=UP")),
+        IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")
     ),
 ]
 
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = [
+    # Feather 0.1" Header Pin Numbers, 
+    # Note: Pin nubering is not continuous.
+    ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"),
+]
+
+# Standard Feather Pins
+feather_serial = [
+    ("serial", 0,
+        Subsignal("tx", Pins("GPIO:1"), IOStandard("LVCMOS33")),
+        Subsignal("rx", Pins("GPIO:0"), IOStandard("LVCMOS33"))
+    )
+]
+
+feather_i2c = [
+    ("i2c", 0,
+        ("sda", Pins("GPIO:2"), IOStandard("LVCMOS33")),
+        ("scl", Pins("GPIO:3"), IOStandard("LVCMOS33"))
+    )
+]
+
+feather_spi = [
+    ("spi",0,
+        ("miso", Pins("GPIO:14"), IOStandard("LVCMOS33")),
+        ("mosi", Pins("GPIO:16"), IOStandard("LVCMOS33")),
+        ("sck", Pins("GPIO:15"), IOStandard("LVCMOS33"))
+    )
+]
+
+
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(LatticePlatform):
     default_clk_name = "clk48"
     default_clk_period = 1e9/48e6
 
-    def __init__(self, **kwargs):
-        LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs)
+    def __init__(self, device='25F', **kwargs):
+        LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs)
diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
index 5a5a613..14528d5 100755
--- a/litex_boards/targets/orangecrab.py
+++ b/litex_boards/targets/orangecrab.py
@@ -57,8 +57,7 @@ class _CRG(Module):
             Instance("ECLKBRIDGECS",
                 i_CLK0   = self.cd_sys2x_i.clk,
                 i_SEL    = 0,
-                o_ECSOUT = sys2x_clk_ecsout,
-            ),
+                o_ECSOUT = sys2x_clk_ecsout),
             Instance("ECLKSYNCB",
                 i_ECLKI = sys2x_clk_ecsout,
                 i_STOP  = self.stop,
@@ -78,13 +77,17 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
         platform = orangecrab.Platform(toolchain=toolchain)
+        
+        # Serial -----------------------------------------------------------------------------------
+        platform.add_extension(orangecrab.feather_serial)
 
-        # SoCCore ----------------------------------------------------------------_-----------------
+        # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = ECP5DDRPHY(
@@ -114,6 +117,8 @@ def main():
     trellis_args(parser)
     parser.add_argument("--sys-clk-freq", default=48e6,
                         help="system clock frequency (default=48MHz)")
+    parser.add_argument("--device", default="25F",
+                        help="ECP5 device (default=25F)")
     args = parser.parse_args()
 
     soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))