diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py
index 45199c0..5bb1cba 100755
--- a/litex_boards/targets/digilent_arty.py
+++ b/litex_boards/targets/digilent_arty.py
@@ -74,7 +74,7 @@ class BaseSoC(SoCCore):
         platform = arty.Platform(variant=variant, toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------
-        with_dram = (kwargs.get("integrated_main_ram_size", 0) != 0)
+        with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
         self.submodules.crg = _CRG(platform, sys_clk_freq, with_dram)
 
         # SoCCore ----------------------------------------------------------------------------------
diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py
index a843b98..16caf0b 100755
--- a/litex_boards/targets/gsd_orangecrab.py
+++ b/litex_boards/targets/gsd_orangecrab.py
@@ -149,12 +149,12 @@ class BaseSoC(SoCCore):
         platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------
-        with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
+        with_usb_pll = kwargs.get("uart_name") in ["serial", "usb_acm"]
         crg_cls      = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG
         self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
 
         # SoCCore ----------------------------------------------------------------------------------
-        if kwargs["uart_name"] in ["serial", "usb_acm"]:
+        if kwargs["uart_name"] in ["serial"]:
             kwargs["uart_name"] = "usb_acm"
             # Defaults to USB ACM through ValentyUSB.
             os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
diff --git a/litex_boards/targets/sipeed_tang_nano.py b/litex_boards/targets/sipeed_tang_nano.py
index ea0e67b..c050258 100755
--- a/litex_boards/targets/sipeed_tang_nano.py
+++ b/litex_boards/targets/sipeed_tang_nano.py
@@ -68,6 +68,7 @@ class BaseSoC(SoCMini):
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
         # SoCMini ----------------------------------------------------------------------------------
+        kwargs["uart_name"] = "crossover"
         SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano", **kwargs)
 
         # UARTBone ---------------------------------------------------------------------------------