From 88f7d5f019b0e26d470923bb30514ff568c8f111 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 8 Oct 2024 13:27:59 +0200 Subject: [PATCH] finix_trion_t20_bga256_dev_kit: fix ClockSignal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Fin Maaß --- litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index 92fe6e2..04db654 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -69,7 +69,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 : - self.specials += ClkOutput(ClockSignal(self.cd_sys_ps), platform.request("sdram_clock")) + self.specials += ClkOutput(ClockSignal("sys_ps"), platform.request("sdram_clock")) self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram",