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finix_trion_t20_bga256_dev_kit: fix ClockSignal 

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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Fin Maaß 2024-10-08 13:27:59 +02:00
parent 77cb9a5c17
commit 88f7d5f019
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1 changed files with 1 additions and 1 deletions
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litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
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@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 : if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
self.specials += ClkOutput(ClockSignal(self.cd_sys_ps), platform.request("sdram_clock")) self.specials += ClkOutput(ClockSignal("sys_ps"), platform.request("sdram_clock"))
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",