From 892bf3546d7933420a6aca21082f5dce76a4b3d4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 15 Nov 2022 15:34:49 +0800 Subject: [PATCH] isx_im1283: connect CRG reset to PLL This fixes soft reset. Signed-off-by: Icenowy Zheng --- litex_boards/targets/isx_im1283.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex_boards/targets/isx_im1283.py b/litex_boards/targets/isx_im1283.py index fa3a805..5cdbc35 100755 --- a/litex_boards/targets/isx_im1283.py +++ b/litex_boards/targets/isx_im1283.py @@ -39,10 +39,12 @@ class _CRG(LiteXModule): # # # self.pll = pll = S7PLL(speedgrade=-2) pll.register_clkin(platform.request("clk200"), 200e6) + self.comb += pll.reset.eq(self.rst) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_idelay, 200e6) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)