From 89dd00d3a233cd6fc56cbe7fa4760e7d84c9c432 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Mar 2020 13:01:36 +0100 Subject: [PATCH] platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms). --- litex_boards/platforms/aller.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/litex_boards/platforms/aller.py b/litex_boards/platforms/aller.py index 4e0fb62..67feb28 100644 --- a/litex_boards/platforms/aller.py +++ b/litex_boards/platforms/aller.py @@ -51,16 +51,6 @@ _io = [ ), # pcie - ("pcie", 0, - Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), - Subsignal("clk_p", Pins("F6")), - Subsignal("clk_n", Pins("E6")), - Subsignal("rx_p", Pins("B8 D11 B10 D9")), - Subsignal("rx_n", Pins("A8 C11 A10 C9")), - Subsignal("tx_p", Pins("B4 D5 B6 D7")), - Subsignal("tx_n", Pins("A4 C5 A6 C7")) - ), - ("pcie_x1", 0, Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("clk_p", Pins("F6")), @@ -71,6 +61,16 @@ _io = [ Subsignal("tx_n", Pins("A4")) ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("F6")), + Subsignal("clk_n", Pins("E6")), + Subsignal("rx_p", Pins("B8 D11 B10 D9")), + Subsignal("rx_n", Pins("A8 C11 A10 C9")), + Subsignal("tx_p", Pins("B4 D5 B6 D7")), + Subsignal("tx_n", Pins("A4 C5 A6 C7")) + ), + # dram ("ddram", 0, Subsignal("a", Pins(