From 8a33c2aa312dddc66297f7cd6e39107fda5a2efb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Jan 2022 19:07:14 +0100 Subject: [PATCH] targets: Ensure litex.soc.cores.spi_flash is no longer imported/used. --- litex_boards/targets/fairwaves_xtrx.py | 2 +- litex_boards/targets/qwertyembedded_beaglewire.py | 5 +++-- litex_boards/targets/sqrl_acorn.py | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py index a78c251..21bffff 100755 --- a/litex_boards/targets/fairwaves_xtrx.py +++ b/litex_boards/targets/fairwaves_xtrx.py @@ -90,7 +90,7 @@ class BaseSoC(SoCCore): self.icap.add_reload() self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - # Flash (For SPIFlash update over PCIe). FIXME: Should probably be updated to use SpiFlashSingle/SpiFlashDualQuad (so MMAPed and do the update with bit-banging) + # Flash (For SPIFlash update over PCIe). from litex.soc.cores.gpio import GPIOOut from litex.soc.cores.spi_flash import S7SPIFlash self.submodules.flash_cs_n = GPIOOut(platform.request("flash_cs_n")) diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py index b57f361..d0aeede 100755 --- a/litex_boards/targets/qwertyembedded_beaglewire.py +++ b/litex_boards/targets/qwertyembedded_beaglewire.py @@ -21,7 +21,6 @@ from litex.soc.cores.clock import iCE40PLL from litex.soc.integration.soc_core import * from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * -from litex.soc.cores.spi_flash import SpiFlash from litex.soc.cores.led import LedChaser from litex.soc.cores.uart import UARTWishboneBridge @@ -92,7 +91,9 @@ class BaseSoC(SoCCore): ) # SPI Flash -------------------------------------------------------------------------------- - self.add_spi_flash(mode="1x", dummy_cycles=8) + from litespi.modules import M25PX32 + from litespi.opcodes import SpiNorFlashOpCodes as Codes + self.add_spi_flash(mode="1x", module=M25PX32(Codes.READ_1_1_1), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py index de9408a..f935fb3 100755 --- a/litex_boards/targets/sqrl_acorn.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -117,7 +117,7 @@ class BaseSoC(SoCCore): self.icap.add_reload() self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - # Flash (For SPIFlash update over PCIe). FIXME: Should probably be updated to use SpiFlashSingle/SpiFlashDualQuad (so MMAPed and do the update with bit-banging) + # Flash (For SPIFlash update over PCIe). from litex.soc.cores.gpio import GPIOOut from litex.soc.cores.spi_flash import S7SPIFlash self.submodules.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))