targets/quicklogic_quickfeather: updated qlal4s3b_cell_macro Clock and Reset signals (similar fix to #1797)

litex_boards/targets/quicklogic_quickfeather.py

@@ -38,10 +38,10 @@ class _CRG(LiteXModule):
             # Use clocks generated by the qlal4s3b_cell_macro.
             class Open(Signal): pass
             self.specials += Instance("qlal4s3b_cell_macro",
-                o_Sys_Clk0     = self.cd_sys.clk,
-                o_Sys_Clk0_Rst = self.cd_sys.rst,
-                o_Sys_Clk1     = Open(),
-                o_Sys_Clk1_Rst = Open(),
+                o_Clk_C16     = self.cd_sys.clk,
+                o_Clk_C16_Rst = self.cd_sys.rst,
+                o_Clk_C21     = Open(),
+                o_Clk_C21_Rst = Open(),
             )
 
 # BaseSoC ------------------------------------------------------------------------------------------