From 8bb3caee5f1aff089388952c94ae4af30911ed91 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 30 May 2024 08:37:14 +0200 Subject: [PATCH] targets/quicklogic_quickfeather: updated qlal4s3b_cell_macro Clock and Reset signals (similar fix to #1797) --- litex_boards/targets/quicklogic_quickfeather.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py index 3bbbae6..ba51d72 100755 --- a/litex_boards/targets/quicklogic_quickfeather.py +++ b/litex_boards/targets/quicklogic_quickfeather.py @@ -38,10 +38,10 @@ class _CRG(LiteXModule): # Use clocks generated by the qlal4s3b_cell_macro. class Open(Signal): pass self.specials += Instance("qlal4s3b_cell_macro", - o_Sys_Clk0 = self.cd_sys.clk, - o_Sys_Clk0_Rst = self.cd_sys.rst, - o_Sys_Clk1 = Open(), - o_Sys_Clk1_Rst = Open(), + o_Clk_C16 = self.cd_sys.clk, + o_Clk_C16_Rst = self.cd_sys.rst, + o_Clk_C21 = Open(), + o_Clk_C21_Rst = Open(), ) # BaseSoC ------------------------------------------------------------------------------------------