diff --git a/litex_boards/platforms/sipeed_tang_mega_138k.py b/litex_boards/platforms/sipeed_tang_mega_138k.py
index d78d3f6..3d82aca 100644
--- a/litex_boards/platforms/sipeed_tang_mega_138k.py
+++ b/litex_boards/platforms/sipeed_tang_mega_138k.py
@@ -51,6 +51,35 @@ _io = [
         IOStandard("LVCMOS33"),
     ),
     ("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")),
+
+    # DDR3 SDRAM IMD128M16R39CG8GNF-125.
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "N1 R1 R2 N2 P1 T2 N4 U1",
+            "T4 T3 M1 P4 N3 U2 U5 M6"),
+            IOStandard("SSTL15")
+        ),
+        Subsignal("ba",      Pins("M4 L5 K3"),    IOStandard("SSTL15")),
+        Subsignal("ras_n",   Pins("H2"),          IOStandard("SSTL15")),
+        Subsignal("cas_n",   Pins("H1"),          IOStandard("SSTL15")),
+        Subsignal("we_n",    Pins("J3"),          IOStandard("SSTL15")),
+        Subsignal("cs_n",    Pins("L4"),          IOStandard("SSTL15")),
+        Subsignal("dm",      Pins("F4 H9 E3 A3"), IOStandard("SSTL15")),
+        Subsignal("dq",      Pins(
+            "G4 J6 L8 G5 K7 J5 K8 K6",
+            "E6 H8 H6 G8 D6 F8 G6 F7",
+            "C4 F3 B4 E5 D3 D5 A4 D4",
+            "E1 A2 G2 C2 F2 E2 G1 D1"),
+            IOStandard("SSTL15")),
+        Subsignal("dqs_p",   Pins("J4 H7 B5 C1"), IOStandard("SSTL15D")), # DRIVE=8
+        Subsignal("dqs_n",   Pins("H4 G7 A5 B1"), IOStandard("SSTL15D")), # DRIVE=8
+        Subsignal("clk_p",   Pins("M2"),          IOStandard("SSTL15D")), # DRIVE=8
+        Subsignal("clk_n",   Pins("L2"),          IOStandard("SSTL15D")), # DRIVE=8
+        Subsignal("cke",     Pins("L3"),          IOStandard("SSTL15")),  # DRIVE=4
+        Subsignal("odt",     Pins("J1"),          IOStandard("SSTL15")),
+        Subsignal("reset_n", Pins("N8"),          IOStandard("SSTL15")),
+        Misc("PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5"),
+    ),
 ]
 
 # Connectors ---------------------------------------------------------------------------------------