diff --git a/litex_boards/platforms/trenz_tec0117.py b/litex_boards/platforms/trenz_tec0117.py
index d007d2d..77166eb 100644
--- a/litex_boards/platforms/trenz_tec0117.py
+++ b/litex_boards/platforms/trenz_tec0117.py
@@ -75,9 +75,33 @@ _io = [
 # Connectors ---------------------------------------------------------------------------------------
 
 _connectors = [
-    ("PMOD", "47 41 38 40 - - 36 42 39 37"),
+    ("pmod", "47 41 38 40 36 42 39 37"),
 ]
 
+# PMODs --------------------------------------------------------------------------------------------
+
+def sdcard_pmod_io(pmod):
+    return [
+        # SDCard PMOD:
+        # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
+        # - https://github.com/antmicro/arty-expansion-board
+        ("spisdcard", 0,
+            Subsignal("clk",  Pins(f"{pmod}:3")),
+            Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULL_MODE=UP")),
+            Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULL_MODE=UP")),
+            Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULL_MODE=UP")),
+            IOStandard("LVCMOS33"),
+        ),
+        ("sdcard", 0,
+            Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULL_MODE=UP")),
+            Subsignal("cmd",  Pins(f"{pmod}:1"), Misc("PULL_MODE=UP")),
+            Subsignal("clk",  Pins(f"{pmod}:3")),
+            Subsignal("cd",   Pins(f"{pmod}:6")),
+            IOStandard("LVCMOS33"),
+        ),
+]
+_sdcard_pmod_io = sdcard_pmod_io("pmod")
+
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(GowinPlatform):
@@ -85,7 +109,7 @@ class Platform(GowinPlatform):
     default_clk_period = 1e9/12e6
 
     def __init__(self):
-        GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, toolchain="gowin", devicename='GW1NR-9')
+        GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, _connectors, toolchain="gowin", devicename='GW1NR-9')
 
     def create_programmer(self):
         return OpenFPGALoader("littlebee")
diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py
index 8c53337..6675514 100755
--- a/litex_boards/targets/trenz_tec0117.py
+++ b/litex_boards/targets/trenz_tec0117.py
@@ -60,8 +60,8 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1",
+    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x00000000}}
+    def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1",
                  with_led_chaser=True, **kwargs):
         platform = tec0117.Platform()
 
@@ -84,7 +84,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.mem_map["spiflash"] + bios_flash_offset,
-            size   = 32*kB,
+            size   = 64*kB,
             linker = True)
         )
 
@@ -110,10 +110,9 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
-                l2_cache_size           = 128,
-                l2_cache_min_data_width = 256,
+                phy           = self.sdrphy,
+                module        = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
+                l2_cache_size = 128,
             )
 
         # Leds -------------------------------------------------------------------------------------
@@ -162,6 +161,9 @@ def main():
     parser.add_argument("--bios-flash-offset", default=0x0000,      help="BIOS offset in SPI Flash (0x00000 default)")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream and BIOS")
     parser.add_argument("--sys-clk-freq",      default=25e6,        help="System clock frequency (default: 25MHz)")
+    sdopts = parser.add_mutually_exclusive_group()
+    sdopts.add_argument("--with-spi-sdcard",     action="store_true", help="Enable SPI-mode SDCard support")
+    sdopts.add_argument("--with-sdcard",         action="store_true", help="Enable SDCard support")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
@@ -171,7 +173,13 @@ def main():
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args)
     )
-    builder = Builder(soc, **builder_argdict(args), bios_options=["TERM_MINI"])
+    soc.platform.add_extension(tec0117._sdcard_pmod_io)
+    if args.with_spi_sdcard:
+        soc.add_spi_sdcard()
+    if args.with_sdcard:
+        soc.add_sdcard()
+
+    builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
     if args.load: