From 8d3aaa8ea9877655a8344d1edd8654c890b34927 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 11 Mar 2021 09:48:26 +0100 Subject: [PATCH] targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done). --- litex_boards/targets/nexys_video.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 317e3bd..1edb084 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -37,6 +37,7 @@ class _CRG(Module): self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain() + self.clock_domains.cd_clk100 = ClockDomain() # # # @@ -52,6 +53,7 @@ class _CRG(Module): pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_hdmi, 40e6) pll.create_clkout(self.cd_hdmi5x, 5*40e6) + pll.create_clkout(self.cd_clk100, 100e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)