diff --git a/litex_boards/platforms/sipeed_tang_nano_4k.py b/litex_boards/platforms/sipeed_tang_nano_4k.py
index 8e5af29..c5d60ca 100644
--- a/litex_boards/platforms/sipeed_tang_nano_4k.py
+++ b/litex_boards/platforms/sipeed_tang_nano_4k.py
@@ -4,6 +4,11 @@
 # Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
+# Board diagram/pinout:
+# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-specifications.jpg
+# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-GW1NSR-4C-FPGA-board-pinout-diagram.jpg
+
+
 from migen import *
 
 from litex.build.generic_platform import *
@@ -15,10 +20,51 @@ from litex.build.openfpgaloader import OpenFPGALoader
 _io = [
     # Clk / Rst
     ("clk27",  0, Pins("45"), IOStandard("LVCMOS33")),
-    ("rst_n",  0, Pins("15"), IOStandard("LVCMOS33")),
 
     # Leds
     ("user_led", 0, Pins("10"), IOStandard("LVCMOS33")),
+
+    # Buttons.
+    ("user_btn", 0, Pins("14"),  IOStandard("LVCMOS18")),
+    ("user_btn", 1, Pins("15"),  IOStandard("LVCMOS18")),
+
+    # SPIFlash
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("2"), IOStandard("LVCMOS33")),
+        Subsignal("clk",  Pins("1"), IOStandard("LVCMOS33")),
+        Subsignal("miso", Pins("47"), IOStandard("LVCMOS33")),
+        Subsignal("mosi", Pins("48"), IOStandard("LVCMOS33")),
+        Subsignal("wp",   Pins("8"), IOStandard("LVCMOS33")),
+        Subsignal("hold", Pins("9"), IOStandard("LVCMOS33")),
+    ),
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("2")),
+        Subsignal("clk",  Pins("1")),
+        Subsignal("dq",   Pins("48 47 8 9")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # HyperRAM (embedded in SIP, requires specific IO naming).
+    ("O_hpram_ck",      0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_hpram_ck_n",    0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_hpram_cs_n",    0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_hpram_reset_n", 0, Pins(1), IOStandard("LVCMOS33")),
+    ("IO_hpram_dq",     0, Pins(8), IOStandard("LVCMOS33")),
+    ("IO_hpram_rwds",   0, Pins(1), IOStandard("LVCMOS33")),
+
+    # HDMI Out.
+    ("hdmi_out", 0,
+        Subsignal("clk_p",   Pins("28")),
+        Subsignal("clk_n",   Pins("27")),
+        Subsignal("data0_p", Pins("30")),
+        Subsignal("data0_n", Pins("29")),
+        Subsignal("data1_p", Pins("32")),
+        Subsignal("data1_n", Pins("31")),
+        Subsignal("data2_p", Pins("35")),
+        Subsignal("data2_n", Pins("34")),
+        Misc("PULL_MODE=NONE"),
+        Misc("DRIVE=3.5"),
+    ),
 ]
 
 # Connectors ---------------------------------------------------------------------------------------
@@ -34,9 +80,11 @@ class Platform(GowinPlatform):
     def __init__(self):
         GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain="gowin", devicename="GW1NSR-4C")
         self.toolchain.options["use_mode_as_gpio"] = 1
+        self.toolchain.options["use_mspi_as_gpio"] = 1
+        self.toolchain.options["use_done_as_gpio"] = 1
 
     def create_programmer(self):
-        return OpenFPGALoader("tangnano")
+        return OpenFPGALoader("tangnano4k")
 
     def do_finalize(self, fragment):
         GowinPlatform.do_finalize(self, fragment)
diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py
index 309d6ff..6d2ea4a 100755
--- a/litex_boards/targets/sipeed_tang_nano_4k.py
+++ b/litex_boards/targets/sipeed_tang_nano_4k.py
@@ -17,7 +17,6 @@ from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
 from litex_boards.platforms import tang_nano_4k
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -29,7 +28,7 @@ class _CRG(Module):
 
         # Clk / Rst
         clk27 = platform.request("clk27")
-        rst_n = platform.request("rst_n")
+        rst_n = platform.request("user_btn", 0)
         self.comb += self.cd_sys.clk.eq(clk27)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
 
@@ -39,6 +38,7 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(27e6), with_led_chaser=True, **kwargs):
         platform = tang_nano_4k.Platform()
 
+
         # Disable CPU/UART for now.
         kwargs["cpu_type"]  = None
         kwargs["with_uart"] = False
@@ -64,7 +64,8 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Tang Nano 4K")
     parser.add_argument("--build",       action="store_true", help="Build bitstream")
     parser.add_argument("--load",        action="store_true", help="Load bitstream")
-    parser.add_argument("--sys-clk-freq",default=27e6,        help="System clock frequency (default: 25MHz)")
+    parser.add_argument("--flash",       action="store_true", help="Flash Bitstream")
+    parser.add_argument("--sys-clk-freq",default=27e6,        help="System clock frequency (default: 27MHz)")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
@@ -81,5 +82,9 @@ def main():
         prog = soc.platform.create_programmer()
         prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
 
+    if args.flash:
+        prog = soc.platform.create_programmer()
+        prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
+
 if __name__ == "__main__":
     main()