diff --git a/litex_boards/platforms/fairwaves_xtrx.py b/litex_boards/platforms/fairwaves_xtrx.py
index a562951..91844d4 100644
--- a/litex_boards/platforms/fairwaves_xtrx.py
+++ b/litex_boards/platforms/fairwaves_xtrx.py
@@ -8,7 +8,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import Xilinx7SeriesPlatform
-from litex.build.openocd import OpenOCD
+from litex.build.openfpgaloader import OpenFPGALoader
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -18,6 +18,7 @@ _io = [
 
     # Leds.
     ("user_led", 0, Pins("N18"),  IOStandard("LVCMOS25")),
+    ("user_led2", 0, Pins("G3 M2 G2"),  IOStandard("LVCMOS33")), # GPIO LED
 
     # PCIe.
     ("pcie_x1", 0,
@@ -40,6 +41,18 @@ _io = [
         Subsignal("tx_n",  Pins("A2 D1")),
     ),
 
+    # USB
+    ("usb", 0,
+        Subsignal("usb_d",    Pins("B17 A17 B16 A16 B15 A15 A14 C15")),
+        Subsignal("usb_stp",  Pins("C17"), Misc("PULLUP=TRUE")),
+        Subsignal("usb_clk",  Pins("C16")),
+        Subsignal("usb_dir",  Pins("B18")),
+        Subsignal("usb_nxt",  Pins("A18")),
+        Subsignal("usb_nrst", Pins("M18"), Misc("PULLDOWN=True")),
+        Subsignal("usb_26m",  Pins("E19")),
+        IOStandard("LVCMOS25")
+    ),
+
     # SPIFlash.
     ("flash_cs_n", 0, Pins("K19"), IOStandard("LVCMOS25")),
     ("flash", 0,
@@ -65,26 +78,47 @@ _io = [
         IOStandard("LVCMOS33"),
     ),
 
+    # XSYNC SPI bus.
+    ("xsync_spi", 1,
+        Subsignal("cs_n", Pins("H1")), # GPIO9
+        Subsignal("clk",  Pins("J1")), # GPIO10
+        Subsignal("mosi", Pins("N3")), # GPIO8
+        IOStandard("LVCMOS33"),
+    ),
+
+    # Synchro.
+    ("synchro", 0,
+        Subsignal("pps_in", Pins("M3")), # GPIO0
+        Subsignal("pps_out",Pins("L3")), # GPIO1
+        IOStandard("LVCMOS33"),
+    ),
+
     # GPS.
     ("gps", 0,
-        Subsignal("rst",    Pins("L18"), IOStandard("LVCMOS25")),
-        Subsignal("pps",    Pins("P3"),  Misc("PULLDOWN=True")),
-        Subsignal("rx" ,    Pins("N2"),  Misc("PULLUP=True")),
-        Subsignal("tx" ,    Pins("L1"),  Misc("PULLUP=True")),
+        Subsignal("rst", Pins("L18"), IOStandard("LVCMOS25")),
+        Subsignal("pps", Pins("P3"),  Misc("PULLDOWN=True")),
+        Subsignal("rx" , Pins("N2"),  Misc("PULLUP=True")),
+        Subsignal("tx" , Pins("L1"),  Misc("PULLUP=True")),
         IOStandard("LVCMOS33")
     ),
 
     # VCTCXO.
     ("vctcxo", 0,
-        Subsignal("sel",    Pins("V17"), Misc("PULLDOWN=True")),
-        Subsignal("clk",    Pins("N17"), Misc("PULLDOWN=True")),
+        Subsignal("en",  Pins("R19"), Misc("PULLUP=True")),
+        Subsignal("sel", Pins("V17"), Misc("PULLDOWN=True")), # ext_clk
+        Subsignal("clk", Pins("N17"), Misc("PULLDOWN=True")),
         IOStandard("LVCMOS25")
     ),
 
-    # GPIO.
-    ("gpio", 0,
+    # GPIO
+    ("gpio", 0, Pins("H2 J2 N3 H1 J1 K2 L2"), IOStandard("LVCMOS33")),
+
+    # AUX.
+    ("aux", 0,
         Subsignal("iovcc_sel",  Pins("V19")),
         Subsignal("en_smsigio", Pins("D17")),
+        Subsignal("option",     Pins("V14")),
+        Subsignal("gpio13",     Pins("T17")),
         IOStandard("LVCMOS25")
     ),
 
@@ -127,6 +161,16 @@ _io = [
         IOStandard("LVCMOS25"),
         Misc("SLEW=FAST"),
     ),
+
+    # SIM.
+    ("sim", 0,
+        Subsignal("mode",    Pins("R3")),
+        Subsignal("enable",  Pins("U1")),
+        Subsignal("clk",     Pins("T1")),
+        Subsignal("reset",   Pins("R2")),
+        Subsignal("data",    Pins("T2")),
+        IOStandard("LVCMOS25")
+    ),
 ]
 
 # Platform -----------------------------------------------------------------------------------------
@@ -135,13 +179,24 @@ class Platform(Xilinx7SeriesPlatform):
     default_clk_name   = "clk60"
     default_clk_period = 1e9/60e6
 
-    def __init__(self, toolchain="vivado"):
+    def __init__(self, variant="xc7a50t", toolchain="vivado"):
+        assert variant in ["xc7a35t", "xc7a50t"]
+        self.variant = variant
+        device = {
+            "xc7a35t" : "xc7a35tcpg236-3",
+            "xc7a50t" : "xc7a50tcpg236-2",
+        }[variant]
         Xilinx7SeriesPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain=toolchain)
 
         self.toolchain.bitstream_commands = [
+            "set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]",
             "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
-            "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
-            "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
+            "set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable [current_design]",
+            "set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
+            "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
+            "set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]",
+            "set_property CFGBVS VCCO [current_design]",
+            "set_property CONFIG_VOLTAGE 3.3 [current_design]",
         ]
         self.toolchain.additional_commands = [
             # Non-Multiboot SPI-Flash bitstream generation.
@@ -160,7 +215,7 @@ class Platform(Xilinx7SeriesPlatform):
         ]
 
     def create_programmer(self):
-        return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit")
+        return OpenFPGALoader(cable="digilent_hs2", fpga_part=f"{self.variant}cpg236", freq=10e6)
 
     def do_finalize(self, fragment):
         Xilinx7SeriesPlatform.do_finalize(self, fragment)