platforms/fairwaves_xtrx: Update with developments from XTRX-Julia project and simplify variants/switch to openFPGALoader.
This commit is contained in:
Florent Kermarrec
parent
f50ee97520
commit
8dea12d48f
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@ -8,7 +8,7 @@
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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@ -18,6 +18,7 @@ _io = [
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# Leds.
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("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")),
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("user_led2", 0, Pins("G3 M2 G2"), IOStandard("LVCMOS33")), # GPIO LED
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# PCIe.
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("pcie_x1", 0,
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@ -40,6 +41,18 @@ _io = [
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Subsignal("tx_n", Pins("A2 D1")),
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),
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# USB
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("usb", 0,
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Subsignal("usb_d", Pins("B17 A17 B16 A16 B15 A15 A14 C15")),
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Subsignal("usb_stp", Pins("C17"), Misc("PULLUP=TRUE")),
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Subsignal("usb_clk", Pins("C16")),
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Subsignal("usb_dir", Pins("B18")),
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Subsignal("usb_nxt", Pins("A18")),
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Subsignal("usb_nrst", Pins("M18"), Misc("PULLDOWN=True")),
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Subsignal("usb_26m", Pins("E19")),
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IOStandard("LVCMOS25")
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),
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# SPIFlash.
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("flash_cs_n", 0, Pins("K19"), IOStandard("LVCMOS25")),
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("flash", 0,
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@ -65,26 +78,47 @@ _io = [
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IOStandard("LVCMOS33"),
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),
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# XSYNC SPI bus.
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("xsync_spi", 1,
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Subsignal("cs_n", Pins("H1")), # GPIO9
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Subsignal("clk", Pins("J1")), # GPIO10
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Subsignal("mosi", Pins("N3")), # GPIO8
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IOStandard("LVCMOS33"),
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),
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# Synchro.
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("synchro", 0,
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Subsignal("pps_in", Pins("M3")), # GPIO0
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Subsignal("pps_out",Pins("L3")), # GPIO1
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IOStandard("LVCMOS33"),
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),
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# GPS.
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("gps", 0,
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Subsignal("rst", Pins("L18"), IOStandard("LVCMOS25")),
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Subsignal("pps", Pins("P3"), Misc("PULLDOWN=True")),
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Subsignal("rx" , Pins("N2"), Misc("PULLUP=True")),
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Subsignal("tx" , Pins("L1"), Misc("PULLUP=True")),
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Subsignal("rst", Pins("L18"), IOStandard("LVCMOS25")),
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Subsignal("pps", Pins("P3"), Misc("PULLDOWN=True")),
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Subsignal("rx" , Pins("N2"), Misc("PULLUP=True")),
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Subsignal("tx" , Pins("L1"), Misc("PULLUP=True")),
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IOStandard("LVCMOS33")
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),
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# VCTCXO.
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("vctcxo", 0,
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Subsignal("sel", Pins("V17"), Misc("PULLDOWN=True")),
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Subsignal("clk", Pins("N17"), Misc("PULLDOWN=True")),
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Subsignal("en", Pins("R19"), Misc("PULLUP=True")),
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Subsignal("sel", Pins("V17"), Misc("PULLDOWN=True")), # ext_clk
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Subsignal("clk", Pins("N17"), Misc("PULLDOWN=True")),
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IOStandard("LVCMOS25")
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),
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# GPIO.
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("gpio", 0,
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# GPIO
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("gpio", 0, Pins("H2 J2 N3 H1 J1 K2 L2"), IOStandard("LVCMOS33")),
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# AUX.
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("aux", 0,
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Subsignal("iovcc_sel", Pins("V19")),
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Subsignal("en_smsigio", Pins("D17")),
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Subsignal("option", Pins("V14")),
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Subsignal("gpio13", Pins("T17")),
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IOStandard("LVCMOS25")
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),
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@ -127,6 +161,16 @@ _io = [
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IOStandard("LVCMOS25"),
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Misc("SLEW=FAST"),
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),
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# SIM.
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("sim", 0,
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Subsignal("mode", Pins("R3")),
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Subsignal("enable", Pins("U1")),
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Subsignal("clk", Pins("T1")),
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Subsignal("reset", Pins("R2")),
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Subsignal("data", Pins("T2")),
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IOStandard("LVCMOS25")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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@ -135,13 +179,24 @@ class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk60"
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default_clk_period = 1e9/60e6
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def __init__(self, toolchain="vivado"):
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def __init__(self, variant="xc7a50t", toolchain="vivado"):
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assert variant in ["xc7a35t", "xc7a50t"]
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self.variant = variant
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device = {
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"xc7a35t" : "xc7a35tcpg236-3",
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"xc7a50t" : "xc7a50tcpg236-2",
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain=toolchain)
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
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"set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]",
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"set_property CFGBVS VCCO [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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]
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self.toolchain.additional_commands = [
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# Non-Multiboot SPI-Flash bitstream generation.
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@ -160,7 +215,7 @@ class Platform(Xilinx7SeriesPlatform):
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]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit")
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return OpenFPGALoader(cable="digilent_hs2", fpga_part=f"{self.variant}cpg236", freq=10e6)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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