From 2cd89cdd1697877c2ad58330c0aba8a263c9f45b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 13 Jun 2024 12:14:03 +0200 Subject: [PATCH] efinix_trion_t20: add sdram MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add sdram of the efinix trion t20 bga256 dev kit. Signed-off-by: Fin Maaß --- .../efinix_trion_t20_bga256_dev_kit.py | 16 ++++++++++++++ .../efinix_trion_t20_bga256_dev_kit.py | 22 ++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py index 9e06752..dfd0a9a 100644 --- a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py @@ -49,6 +49,22 @@ _io = [ Subsignal("miso", Pins("N1")), IOStandard("3.3_V_LVTTL_/_LVCMOS") ), + + # SDRAM NDS36PT5-20ET + ("sdram_clock", 0, Pins("P16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("SLEW=FAST")), + ("sdram", 0, + Subsignal("a", Pins("C12 D11 C11 E11 J13 J14 J15 K12 K14 L15 D12 L16 M12")), + Subsignal("dq", Pins("B14 A14 B13 A13 B12 B11 A11 B10 K15 E16 D16 C16 C15 B16 B15 A15")), + Subsignal("ba", Pins("C14 C13")), + Subsignal("dm", Pins("K16 B9")), + Subsignal("ras_n", Pins("E12")), + Subsignal("cas_n", Pins("H12")), + Subsignal("we_n", Pins("J12")), + Subsignal("cs_n", Pins("D13")), + Subsignal("cke", Pins("M16")), + IOStandard("3.3_V_LVTTL_/_LVCMOS"), + Misc("SLEW = FAST") + ), ] # Bank voltage --------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index beb15c0..fbab632 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -15,6 +15,7 @@ from litex.gen import * from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit +from litex.build.io import ClkOutput from litex.build.generic_platform import * from litex.soc.cores.clock import * @@ -22,12 +23,18 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser +from litedram.modules import NDS36PT5 +from litedram.phy import GENSDRPHY + # CRG ---------------------------------------------------------------------------------------------- class _CRG(LiteXModule): + name_sdram_clk = "sdram_clk" + def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.cd_sys = ClockDomain() + self.cd_sys_ps = ClockDomain() # # # @@ -39,6 +46,7 @@ class _CRG(LiteXModule): self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name=self.name_sdram_clk) # BaseSoC ------------------------------------------------------------------------------------------ @@ -52,6 +60,18 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", **kwargs) + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 : + self.specials += ClkOutput(self.crg.name_sdram_clk, platform.request("sdram_clock")) + + self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) + self.add_sdram("sdram", + phy = self.sdrphy, + module = NDS36PT5(sys_clk_freq, "1:1"), + l2_cache_size = kwargs.get("l2_size", 8192), + with_bist = kwargs.get("with_bist", False) + ) + # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import W25Q32JV @@ -70,7 +90,7 @@ def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_trion_t20_bga256_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit.") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") - parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") + parser.add_target_argument("--sys-clk-freq", default=45e6, type=float, help="System clock frequency.") parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).") args = parser.parse_args()