From 8f1350ec404d67b5b730cfccc4f902ecf93907a1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 20 Sep 2024 13:09:48 +0200 Subject: [PATCH] targets/digilent_netfpga_sume.py: Limit mapped SDRAM size as on other targets. --- litex_boards/targets/digilent_netfpga_sume.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/digilent_netfpga_sume.py b/litex_boards/targets/digilent_netfpga_sume.py index e7f00f9..c74db5d 100755 --- a/litex_boards/targets/digilent_netfpga_sume.py +++ b/litex_boards/targets/digilent_netfpga_sume.py @@ -74,11 +74,12 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq - ) + ) self.add_sdram("sdram", phy = self.ddrphy, module = MT8KTF51264(sys_clk_freq, "1:4"), - l2_cache_size = kwargs.get("l2_size", 8192) + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192), ) # Ethernet / Etherbone ---------------------------------------------------------------------