targets/digilent_netfpga_sume.py: Limit mapped SDRAM size as on other targets.

2024-09-20 13:09:48 +02:00 · 2024-09-20 13:09:48 +02:00 · 8f1350ec40
parent 223367d6b6
commit 8f1350ec40
1 changed files with 3 additions and 2 deletions
--- a/litex_boards/targets/digilent_netfpga_sume.py
+++ b/litex_boards/targets/digilent_netfpga_sume.py
@ -78,7 +78,8 @@ class BaseSoC(SoCCore):
             self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT8KTF51264(sys_clk_freq, "1:4"),
-                l2_cache_size = kwargs.get("l2_size", 8192)
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192),
            )
            
        # Ethernet / Etherbone ---------------------------------------------------------------------