Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/enclustra: Add Enclustra to identifier.

This commit is contained in:
Florent Kermarrec 2024-07-22 11:38:22 +02:00
parent f844d06da2
commit 8f8e0bd228
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/targets/enclustra_mercury_kx2.py
View File

@ -56,7 +56,7 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KX2", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Enclustra Mercury+ KX2", **kwargs)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
@ -80,7 +80,7 @@ class BaseSoC(SoCCore):
def main(): def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=enclustra_mercury_kx2.Platform, description="LiteX SoC on KX2.") parser = LiteXArgumentParser(platform=enclustra_mercury_kx2.Platform, description="LiteX SoC on Enclustra Mercury+ KX2.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_argument("--with-st1-baseboard", action="store_true", help="add enclustra ST1 baseboard") parser.add_argument("--with-st1-baseboard", action="store_true", help="add enclustra ST1 baseboard")
args = parser.parse_args() args = parser.parse_args()

4
litex_boards/targets/enclustra_mercury_xu5.py
View File

@ -60,7 +60,7 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mercury XU5", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Enclustra Mercury XU5", **kwargs)
# DDR4 SDRAM ------------------------------------------------------------------------------- # DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
@ -84,7 +84,7 @@ class BaseSoC(SoCCore):
def main(): def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=enclustra_mercury_xu5.Platform, description="LiteX SoC on Mercury XU5.") parser = LiteXArgumentParser(platform=enclustra_mercury_xu5.Platform, description="LiteX SoC on Enclustra Mercury XU5.")
parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
args = parser.parse_args() args = parser.parse_args()