From 8f9d735630c960e3d3fb4a2d25fd40fc0a5e8e24 Mon Sep 17 00:00:00 2001
From: Hans Baier <hansfbaier@gmail.com>
Date: Tue, 16 May 2023 03:03:30 +0700
Subject: [PATCH] fix comment

---
 litex_boards/platforms/pcbarts_klusterlab.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/litex_boards/platforms/pcbarts_klusterlab.py b/litex_boards/platforms/pcbarts_klusterlab.py
index 02766b3..cc2a535 100644
--- a/litex_boards/platforms/pcbarts_klusterlab.py
+++ b/litex_boards/platforms/pcbarts_klusterlab.py
@@ -75,8 +75,7 @@ _io = [
         Subsignal("sys",  Pins("C19")),
         IOStandard("LVCMOS33")),
 
-    # The Serial which connects to the second UART
-    # of the FTDI on the base board (first FTDI port is JTAG)
+    # USB Serial
     ("serial", 0,
         Subsignal("tx",  Pins("A17")),
         Subsignal("rx",  Pins("K15")),