From 8fa3f09226a6ae249e636e57f58c3dd2904f93f6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Dec 2019 15:22:40 +0100 Subject: [PATCH] partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices. --- litex_boards/partner/targets/c10lprefkit.py | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py index 5ed1d8f..4ebd342 100755 --- a/litex_boards/partner/targets/c10lprefkit.py +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -77,6 +77,8 @@ class _CRG(Module): self.comb += self.cd_sys.clk.eq(clk_outs[0]) self.comb += self.cd_sys_ps.clk.eq(clk_outs[1]) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + platform.add_period_constraint(self.cd_sys.clk, 1e9/50e6) + platform.add_period_constraint(self.cd_sys_ps.clk, 1e9/50e6) # BaseSoC ------------------------------------------------------------------------------------------ @@ -133,14 +135,17 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").tx, 1e9/12.5e6) - self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").rx, 1e9/12.5e6) + self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") + self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( - self.platform.lookup_request("clk12"), - self.platform.lookup_request("eth_clocks").tx, - self.platform.lookup_request("eth_clocks").rx + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_tx.clk, + self.ethphy.crg.cd_eth_rx.clk ) + # Build -------------------------------------------------------------------------------------------- def main():