From 901942bda62f441a8ae4ae3b9d1bb87f1158a613 Mon Sep 17 00:00:00 2001 From: John Simons Date: Thu, 24 Mar 2022 07:39:14 -0700 Subject: [PATCH] Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================-- CPU:BUS:E 32-bit @ 4GiB CSR:16-bit @ 48MT/s (CL-2 CWL-2) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 13.6MiB/s Read speed: 21.3MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. --- .../platforms/arduino_mkrvidor4000.py | 308 ++++++------------ litex_boards/targets/arduino_mkrvidor4000.py | 7 +- 2 files changed, 104 insertions(+), 211 deletions(-) diff --git a/litex_boards/platforms/arduino_mkrvidor4000.py b/litex_boards/platforms/arduino_mkrvidor4000.py index a05f286..21e8091 100644 --- a/litex_boards/platforms/arduino_mkrvidor4000.py +++ b/litex_boards/platforms/arduino_mkrvidor4000.py @@ -11,46 +11,108 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- +_io = [ + # Clk / Rst + ("clk48", 0, Pins("E2"), IOStandard("3.3-V LVTTL")), + + # SDR SDRAM + ("sdram_clock", 0, Pins("B14"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins( + "A12 B12 A15 A14 D14 C14 D11 D12", + "E11 C9 B13 E10 ")), + Subsignal("ba", Pins("A10 B10")), + Subsignal("cs_n", Pins("A11")), + Subsignal("cke", Pins("E9")), + Subsignal("ras_n", Pins("D9")), + Subsignal("cas_n", Pins("B7")), + Subsignal("we_n", Pins("B11")), + Subsignal("dq", Pins( + "A2 B4 B3 A3 A4 A5 B5 A6", + "F8 C8 E7 E8 E6 D8 D6 B6")), + Subsignal("dm", Pins("A7 F9")), + + Misc("FAST_OUTPUT_REGISTER ON"), + + IOStandard("3.3-V LVTTL") + ), + + # # SPIFlash (W25Q64) + # ("spiflash", 0, + # # clk + # Subsignal("cs_n", Pins("E2")), + # Subsignal("clk", Pins("K2")), + # Subsignal("mosi", Pins("D1")), + # Subsignal("miso", Pins("E2")), + # IOStandard("3.3-V LVTTL"), + # ), + + # Serial + ("serial", 0, + Subsignal("tx", Pins("G1"), IOStandard("3.3-V LVTTL")), # User I/O port on Mister + Subsignal("rx", Pins("N3"), IOStandard("3.3-V LVTTL")) # User I/O port on Mister + ), + +# # USB FIFO +# ("usb_fifo", 0, +# Subsignal("dq", Pins("AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"), IOStandard("LVCMOS33")), +# Subsignal("txe_n", Pins("AM31"), IOStandard("LVCMOS33")), +# Subsignal("rxf_n", Pins("AJ31"), IOStandard("LVCMOS33")), +# Subsignal("rd_n", Pins("AL32"), IOStandard("LVCMOS33")), +# Subsignal("wr_n", Pins("AG28"), IOStandard("LVCMOS33")), +# Subsignal("siwu_n", Pins("AJ28"), IOStandard("LVCMOS33")), +# ), + + +# # PCIe +# ("pcie_x1", 0, +# Subsignal("clk_p", Pins("AM14")), +# Subsignal("clk_n", Pins("AM15")), +# Subsignal("rx_p", Pins("AM8 AK12")), +# Subsignal("rx_n", Pins("AM9 AK13")), +# Subsignal("tx_p", Pins("AK9 AM11")), +# Subsignal("tx_n", Pins("AK10 AM12")), +# Subsignal("perst", Pins("D22"), IOStandard("LVCMOS33")), +# Subsignal("wake_n", Pins("A23"), IOStandard("LVCMOS33")), +# ), + + +# # SPIFlash +# ("spiflash", 0, +# Subsignal("clk", Pins("AM3")), +# Subsignal("cs_n", Pins("AJ3")), +# Subsignal("mosi", Pins("AK2")), +# Subsignal("miso", Pins("AJ2")), +# Subsignal("wp", Pins("AM2")), +# Subsignal("hold", Pins("AL1")), +# IOStandard("LVCMOS33") +# ), + + + +# # HDMI +# ("hdmi", 0, +# Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), +# Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), +# Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")), +# Subsignal("tx_clk", Pins("AG5")), +# Subsignal("tx_de", Pins("AD19")), +# Subsignal("tx_hs", Pins("T8")), +# Subsignal("tx_vs", Pins("V13")), +# Subsignal("tx_int", Pins("AF11")), +# Misc("FAST_OUTPUT_REGISTER ON"), +# IOStandard("3.3-V LVTTL") +# ), + +# # I2C +# ("i2c", 0, +# Subsignal("scl", Pins("U10")), +# Subsignal("sda", Pins("AA4")), +# IOStandard("3.3-V LVTTL") +# ), + + ''' -# SDRAM -set_location_assignment PIN_E10 -to oSDRAM_ADDR[11] -set_location_assignment PIN_B13 -to oSDRAM_ADDR[10] -set_location_assignment PIN_C9 -to oSDRAM_ADDR[9] -set_location_assignment PIN_E11 -to oSDRAM_ADDR[8] -set_location_assignment PIN_D12 -to oSDRAM_ADDR[7] -set_location_assignment PIN_D11 -to oSDRAM_ADDR[6] -set_location_assignment PIN_C14 -to oSDRAM_ADDR[5] -set_location_assignment PIN_D14 -to oSDRAM_ADDR[4] -set_location_assignment PIN_A14 -to oSDRAM_ADDR[3] -set_location_assignment PIN_A15 -to oSDRAM_ADDR[2] -set_location_assignment PIN_B12 -to oSDRAM_ADDR[1] -set_location_assignment PIN_A12 -to oSDRAM_ADDR[0] -set_location_assignment PIN_B10 -to oSDRAM_BA[1] -set_location_assignment PIN_A10 -to oSDRAM_BA[0] -set_location_assignment PIN_B7 -to oSDRAM_CASn -set_location_assignment PIN_E9 -to oSDRAM_CKE -set_location_assignment PIN_A11 -to oSDRAM_CSn -set_location_assignment PIN_B6 -to bSDRAM_DQ[15] -set_location_assignment PIN_D6 -to bSDRAM_DQ[14] -set_location_assignment PIN_D8 -to bSDRAM_DQ[13] -set_location_assignment PIN_E6 -to bSDRAM_DQ[12] -set_location_assignment PIN_E8 -to bSDRAM_DQ[11] -set_location_assignment PIN_E7 -to bSDRAM_DQ[10] -set_location_assignment PIN_C8 -to bSDRAM_DQ[9] -set_location_assignment PIN_F8 -to bSDRAM_DQ[8] -set_location_assignment PIN_A6 -to bSDRAM_DQ[7] -set_location_assignment PIN_B5 -to bSDRAM_DQ[6] -set_location_assignment PIN_A5 -to bSDRAM_DQ[5] -set_location_assignment PIN_A4 -to bSDRAM_DQ[4] -set_location_assignment PIN_A3 -to bSDRAM_DQ[3] -set_location_assignment PIN_B3 -to bSDRAM_DQ[2] -set_location_assignment PIN_B4 -to bSDRAM_DQ[1] -set_location_assignment PIN_A2 -to bSDRAM_DQ[0] -set_location_assignment PIN_F9 -to oSDRAM_DQM[1] -set_location_assignment PIN_A7 -to oSDRAM_DQM[0] -set_location_assignment PIN_D9 -to oSDRAM_RASn -set_location_assignment PIN_B14 -to oSDRAM_CLK -set_location_assignment PIN_B11 -to oSDRAM_WEn # SAM D21 PINS set_location_assignment PIN_B1 -to bMKR_AREF @@ -156,176 +218,8 @@ set_location_assignment PIN_N2 -to oSAM_INT set_location_assignment PIN_L16 -to iSAM_INT set_instance_assignment -name IO_STANDARD "2.5 V" -to oSAM_INT set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to iSAM_INT - - -set_location_assignment PIN_E10 -to oSDRAM_ADDR[11] -set_location_assignment PIN_B13 -to oSDRAM_ADDR[10] -set_location_assignment PIN_C9 -to oSDRAM_ADDR[9] -set_location_assignment PIN_E11 -to oSDRAM_ADDR[8] -set_location_assignment PIN_D12 -to oSDRAM_ADDR[7] -set_location_assignment PIN_D11 -to oSDRAM_ADDR[6] -set_location_assignment PIN_C14 -to oSDRAM_ADDR[5] -set_location_assignment PIN_D14 -to oSDRAM_ADDR[4] -set_location_assignment PIN_A14 -to oSDRAM_ADDR[3] -set_location_assignment PIN_A15 -to oSDRAM_ADDR[2] -set_location_assignment PIN_B12 -to oSDRAM_ADDR[1] -set_location_assignment PIN_A12 -to oSDRAM_ADDR[0] -set_location_assignment PIN_B10 -to oSDRAM_BA[1] -set_location_assignment PIN_A10 -to oSDRAM_BA[0] - -set_location_assignment PIN_B7 -to oSDRAM_CASn -set_location_assignment PIN_E9 -to oSDRAM_CKE -set_location_assignment PIN_A11 -to oSDRAM_CSn - -set_location_assignment PIN_B6 -to bSDRAM_DQ[15] -set_location_assignment PIN_D6 -to bSDRAM_DQ[14] -set_location_assignment PIN_D8 -to bSDRAM_DQ[13] -set_location_assignment PIN_E6 -to bSDRAM_DQ[12] -set_location_assignment PIN_E8 -to bSDRAM_DQ[11] -set_location_assignment PIN_E7 -to bSDRAM_DQ[10] -set_location_assignment PIN_C8 -to bSDRAM_DQ[9] -set_location_assignment PIN_F8 -to bSDRAM_DQ[8] - -set_location_assignment PIN_A6 -to bSDRAM_DQ[7] -set_location_assignment PIN_B5 -to bSDRAM_DQ[6] -set_location_assignment PIN_A5 -to bSDRAM_DQ[5] -set_location_assignment PIN_A4 -to bSDRAM_DQ[4] -set_location_assignment PIN_A3 -to bSDRAM_DQ[3] -set_location_assignment PIN_B3 -to bSDRAM_DQ[2] -set_location_assignment PIN_B4 -to bSDRAM_DQ[1] -set_location_assignment PIN_A2 -to bSDRAM_DQ[0] - -set_location_assignment PIN_F9 -to oSDRAM_DQM[1] -set_location_assignment PIN_A7 -to oSDRAM_DQM[0] - -set_location_assignment PIN_D9 -to oSDRAM_RASn -set_location_assignment PIN_B14 -to oSDRAM_CLK -set_location_assignment PIN_B11 -to oSDRAM_WEn ''' - -_io = [ - # Clk / Rst - ("clk48", 0, Pins("E2"), IOStandard("3.3-V LVTTL")), - - # SDR SDRAM - ("sdram_clock", 0, Pins("B14"), IOStandard("3.3-V LVTTL")), - ("sdram", 0, - Subsignal("a", Pins( - "A12 B12 A15 A14 D14 C14 D11 D12", - "E11 C9 B13 E10 ")), - Subsignal("ba", Pins("A10 B10")), - Subsignal("cs_n", Pins("A11")), - Subsignal("cke", Pins("E9")), - Subsignal("ras_n", Pins("D9")), - Subsignal("cas_n", Pins("B7")), - Subsignal("we_n", Pins("B11")), - Subsignal("dq", Pins( - "A2 B4 B3 A3 A4 A5 B5 A6", - "F8 C8 E7 E8 E6 D8 D6 B6")), - Subsignal("dm", Pins("A7 F9")), - - Misc("FAST_OUTPUT_REGISTER ON"), - - IOStandard("3.3-V LVTTL") - ), - - # # SPIFlash (W25Q64) - # ("spiflash", 0, - # # clk - # Subsignal("cs_n", Pins("E2")), - # Subsignal("clk", Pins("K2")), - # Subsignal("mosi", Pins("D1")), - # Subsignal("miso", Pins("E2")), - # IOStandard("3.3-V LVTTL"), - # ), - - # Serial - ("serial", 0, - Subsignal("tx", Pins("G1"), IOStandard("3.3-V LVTTL")), # User I/O port on Mister - Subsignal("rx", Pins("N3"), IOStandard("3.3-V LVTTL")) # User I/O port on Mister - ), - -# # USB FIFO -# ("usb_fifo", 0, -# Subsignal("dq", Pins("AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"), IOStandard("LVCMOS33")), -# Subsignal("txe_n", Pins("AM31"), IOStandard("LVCMOS33")), -# Subsignal("rxf_n", Pins("AJ31"), IOStandard("LVCMOS33")), -# Subsignal("rd_n", Pins("AL32"), IOStandard("LVCMOS33")), -# Subsignal("wr_n", Pins("AG28"), IOStandard("LVCMOS33")), -# Subsignal("siwu_n", Pins("AJ28"), IOStandard("LVCMOS33")), -# ), - - -# # PCIe -# ("pcie_x2", 0, -# Subsignal("clk_p", Pins("AM14")), -# Subsignal("clk_n", Pins("AM15")), -# Subsignal("rx_p", Pins("AM8 AK12")), -# Subsignal("rx_n", Pins("AM9 AK13")), -# Subsignal("tx_p", Pins("AK9 AM11")), -# Subsignal("tx_n", Pins("AK10 AM12")), -# Subsignal("perst", Pins("D22"), IOStandard("LVCMOS33")), -# Subsignal("wake_n", Pins("A23"), IOStandard("LVCMOS33")), -# ), - -# # M2 -# ("m2", 0, -# Subsignal("clk_p", Pins("AM23")), -# Subsignal("clk_n", Pins("AM24")), -# Subsignal("rx_p", Pins("AM17 AK21")), -# Subsignal("rx_n", Pins("AM18 AK22")), -# Subsignal("tx_p", Pins("AK18 AM20")), -# Subsignal("tx_n", Pins("AK19 AM21")), - -# Subsignal("clksel", Pins("N3"), IOStandard("LVCMOS33")), - -# Subsignal("sdio_clk", Pins("L4"), IOStandard("LVCMOS33")), -# Subsignal("sdio_cmd", Pins("K4"), IOStandard("LVCMOS33")), -# Subsignal("sdio_dq", Pins("L7 N4 L6 N6"), IOStandard("LVCMOS33")), - -# Subsignal("uart_tx", Pins("P6"), IOStandard("LVCMOS33")), -# Subsignal("uart_rx", Pins("K5"), IOStandard("LVCMOS33")), -# Subsignal("uart_rts_n", Pins("N7"), IOStandard("LVCMOS33")), -# Subsignal("uart_cts_n", Pins("P7"), IOStandard("LVCMOS33")) -# ), - -# # SPIFlash -# ("spiflash", 0, -# Subsignal("clk", Pins("AM3")), -# Subsignal("cs_n", Pins("AJ3")), -# Subsignal("mosi", Pins("AK2")), -# Subsignal("miso", Pins("AJ2")), -# Subsignal("wp", Pins("AM2")), -# Subsignal("hold", Pins("AL1")), -# IOStandard("LVCMOS33") -# ), - - - -# # HDMI -# ("hdmi", 0, -# Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), -# Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), -# Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")), -# Subsignal("tx_clk", Pins("AG5")), -# Subsignal("tx_de", Pins("AD19")), -# Subsignal("tx_hs", Pins("T8")), -# Subsignal("tx_vs", Pins("V13")), -# Subsignal("tx_int", Pins("AF11")), -# Misc("FAST_OUTPUT_REGISTER ON"), -# IOStandard("3.3-V LVTTL") -# ), - -# # I2C -# ("i2c", 0, -# Subsignal("scl", Pins("U10")), -# Subsignal("sda", Pins("AA4")), -# IOStandard("3.3-V LVTTL") -# ), - - - ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/arduino_mkrvidor4000.py b/litex_boards/targets/arduino_mkrvidor4000.py index 79c0d2e..e338a54 100755 --- a/litex_boards/targets/arduino_mkrvidor4000.py +++ b/litex_boards/targets/arduino_mkrvidor4000.py @@ -13,8 +13,6 @@ from migen import * from litex_boards.platforms import arduino_mkrvidor4000 -from litex.build.io import DDROutput - from litex.soc.cores.clock import Cyclone10LPPLL from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * @@ -57,7 +55,8 @@ class BaseSoC(SoCCore): ident = "LiteX SoC on MKR Vidor 4000", **kwargs) - + self.add_jtagbone() # TODO: untested + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -66,7 +65,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = AS4C4M16(sys_clk_freq, "1:1"), # Winbond W9864G6JT + module = AS4C4M16(sys_clk_freq, "1:1"), # Alliance Memory AS4C4M16 l2_cache_size = kwargs.get("l2_size", 8192) )