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targets/nexys4ddr: fix typo

This commit is contained in:
Florent Kermarrec 2020-01-17 13:15:22 +01:00
parent bb99a8dd0c
commit 908539d49f
1 changed files with 1 additions and 1 deletions
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litex_boards/official/targets/nexys4ddr.py
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@ -79,7 +79,7 @@ class EthernetSoC(BaseSoC):
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------
# phy # phy
self.submodules.ethphy = LiteEthPHYMII( self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth")) pads = self.platform.request("eth"))
self.add_csr("ethphy") self.add_csr("ethphy")