From 917ae333513d48cb6c245612019f5ef091ce6d25 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
Date: Fri, 29 Mar 2024 07:11:06 +0100
Subject: [PATCH] targets/xilinx_zc706: temporary disabled ddr3

---
 litex_boards/targets/xilinx_zc706.py | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/litex_boards/targets/xilinx_zc706.py b/litex_boards/targets/xilinx_zc706.py
index ff589a3..1c3fe02 100755
--- a/litex_boards/targets/xilinx_zc706.py
+++ b/litex_boards/targets/xilinx_zc706.py
@@ -89,16 +89,16 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs)
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
-        if not self.integrated_main_ram_size:
-            self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
-                memtype      = "DDR3",
-                nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
-            self.add_sdram("sdram",
-                phy           = self.ddrphy,
-                module        = MT8JTF12864(sys_clk_freq, "1:4"),
-                l2_cache_size = kwargs.get("l2_size", 8192)
-            )
+        #if not self.integrated_main_ram_size:
+        #    self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
+        #        memtype      = "DDR3",
+        #        nphases      = 4,
+        #        sys_clk_freq = sys_clk_freq)
+        #    self.add_sdram("sdram",
+        #        phy           = self.ddrphy,
+        #        module        = MT8JTF12864(sys_clk_freq, "1:4"),
+        #        l2_cache_size = kwargs.get("l2_size", 8192)
+        #    )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet or with_etherbone: