From 91aff9816dcc1661c1ba6e8e1559f1c4aefaa14f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 Mar 2024 18:30:18 +0100 Subject: [PATCH] targets/litex_acorn_baseboard_mini: Add with_dram parameter to allow build without DRAM. --- .../targets/litex_acorn_baseboard_mini.py | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/litex_boards/targets/litex_acorn_baseboard_mini.py b/litex_boards/targets/litex_acorn_baseboard_mini.py index 225061b..175d3b8 100755 --- a/litex_boards/targets/litex_acorn_baseboard_mini.py +++ b/litex_boards/targets/litex_acorn_baseboard_mini.py @@ -49,7 +49,7 @@ _serial_io = [ # CRG ---------------------------------------------------------------------------------------------- class CRG(LiteXModule): - def __init__(self, platform, sys_clk_freq, with_eth=False): + def __init__(self, platform, sys_clk_freq, with_dram=False, with_eth=False): self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys4x = ClockDomain() @@ -66,13 +66,15 @@ class CRG(LiteXModule): self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk200_se, 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + if with_dram: + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. # IDelayCtrl. - self.comb += self.cd_idelay.clk.eq(clk200_se) - self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + if with_dram: + self.comb += self.cd_idelay.clk.eq(clk200_se) + self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # Eth PLL. if with_eth: @@ -97,12 +99,15 @@ class BaseSoC(SoCCore): platform = Platform(variant=variant) platform.add_extension(_serial_io, prepend=True) - # CRG -------------------------------------------------------------------------------------- - self.crg = CRG(platform, sys_clk_freq, with_eth=with_ethernet or with_etherbone) - # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE-101/215(+)", **kwargs) + # CRG -------------------------------------------------------------------------------------- + self.crg = CRG(platform, sys_clk_freq, + with_dram = not self.integrated_main_ram_size, + with_eth = with_ethernet or with_etherbone, + ) + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),