targets/litex_acorn_baseboard_mini: Add with_dram parameter to allow build without DRAM.

litex_boards/targets/litex_acorn_baseboard_mini.py

@@ -49,7 +49,7 @@ _serial_io = [
 # CRG ----------------------------------------------------------------------------------------------
 
 class CRG(LiteXModule):
-    def __init__(self, platform, sys_clk_freq, with_eth=False):
+    def __init__(self, platform, sys_clk_freq, with_dram=False, with_eth=False):
         self.rst          = Signal()
         self.cd_sys       = ClockDomain()
         self.cd_sys4x     = ClockDomain()
@@ -66,11 +66,13 @@ class CRG(LiteXModule):
         self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk200_se, 200e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
+        if with_dram:
             pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
             pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         # IDelayCtrl.
+        if with_dram:
             self.comb += self.cd_idelay.clk.eq(clk200_se)
             self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
@@ -97,12 +99,15 @@ class BaseSoC(SoCCore):
         platform = Platform(variant=variant)
         platform.add_extension(_serial_io, prepend=True)
 
-        # CRG --------------------------------------------------------------------------------------
-        self.crg = CRG(platform, sys_clk_freq, with_eth=with_ethernet or with_etherbone)
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE-101/215(+)", **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = CRG(platform, sys_clk_freq,
+            with_dram = not self.integrated_main_ram_size,
+            with_eth  = with_ethernet or with_etherbone,
+        )
+
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),