From 346621b9fc71e13af248bbfe59665850d72e7a9c Mon Sep 17 00:00:00 2001 From: Rohit Singh Date: Sun, 1 Sep 2019 03:02:04 -0500 Subject: [PATCH 1/8] partner: add platforms and targets for aller, tagus and nereid boards --- litex_boards/partner/platforms/__init__.py | 3 + litex_boards/partner/platforms/aller.py | 120 ++++++ litex_boards/partner/platforms/nereid.py | 408 +++++++++++++++++++++ litex_boards/partner/platforms/tagus.py | 169 +++++++++ litex_boards/partner/targets/__init__.py | 3 + litex_boards/partner/targets/aller.py | 209 +++++++++++ litex_boards/partner/targets/nereid.py | 224 +++++++++++ litex_boards/partner/targets/tagus.py | 206 +++++++++++ 8 files changed, 1342 insertions(+) create mode 100644 litex_boards/partner/platforms/aller.py create mode 100644 litex_boards/partner/platforms/nereid.py create mode 100644 litex_boards/partner/platforms/tagus.py create mode 100755 litex_boards/partner/targets/aller.py create mode 100755 litex_boards/partner/targets/nereid.py create mode 100755 litex_boards/partner/targets/tagus.py diff --git a/litex_boards/partner/platforms/__init__.py b/litex_boards/partner/platforms/__init__.py index e52d5a6..d5aef64 100644 --- a/litex_boards/partner/platforms/__init__.py +++ b/litex_boards/partner/platforms/__init__.py @@ -1,7 +1,10 @@ +from litex_boards.partner.platforms import aller from litex_boards.partner.platforms import fomu_evt from litex_boards.partner.platforms import fomu_hacker from litex_boards.partner.platforms import fomu_pvt +from litex_boards.partner.platforms import nereid from litex_boards.partner.platforms import netv2 +from litex_boards.partner.platforms import tagus from litex_boards.partner.platforms import tinyfpga_bx from litex_boards.partner.platforms import trellisboard from litex_boards.partner.platforms import ulx3s diff --git a/litex_boards/partner/platforms/aller.py b/litex_boards/partner/platforms/aller.py new file mode 100644 index 0000000..112d184 --- /dev/null +++ b/litex_boards/partner/platforms/aller.py @@ -0,0 +1,120 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Rohit Singh +# License: BSD + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # clk / rst + ("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")), + + # leds (only a single rgb led, aliased here also) + ("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("U20"), IOStandard("LVCMOS33")), + + # rgb led, active-low + ("rgb_led", 0, + Subsignal("r", Pins("AB21")), + Subsignal("g", Pins("AB22")), + Subsignal("b", Pins("U20")), + IOStandard("LVCMOS33"), + ), + + # flash + ("flash", 0, + Subsignal("cs_n", Pins("T19")), + Subsignal("mosi", Pins("P22")), + Subsignal("miso", Pins("R22")), + Subsignal("hold", Pins("R21")), + Subsignal("rst_n", Pins("R19")), + IOStandard("LVCMOS33") + ), + + ("flash4x", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("T19")), + Subsignal("dq", Pins("P22", "R22", "P21", "R21")), + IOStandard("LVCMOS33") + ), + + # tpm + ("tpm", 0, + Subsignal("clk", Pins("W20")), + Subsignal("rst_n", Pins("V19")), + Subsignal("cs_n", Pins("Y18")), + Subsignal("mosi", Pins("Y19")), + Subsignal("miso", Pins("V18")), + IOStandard("LVCMOS33"), + ), + + # pcie + ("pcie", 0, + Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("F6")), + Subsignal("clk_n", Pins("E6")), + Subsignal("rx_p", Pins("B8 D11 B10 D9")), + Subsignal("rx_n", Pins("A8 C11 A10 C9")), + Subsignal("tx_p", Pins("B4 D5 B6 D7")), + Subsignal("tx_n", Pins("A4 C5 A6 C7")) + ), + + ("pcie_x1", 0, + Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("F6")), + Subsignal("clk_n", Pins("E6")), + Subsignal("rx_p", Pins("B8")), + Subsignal("rx_n", Pins("A8")), + Subsignal("tx_p", Pins("B4")), + Subsignal("tx_n", Pins("A4")) + ), + + # dram + ("ddram", 0, + Subsignal("a", Pins( + "U6 T5 Y6 T6 V2 T4 Y2 R2", + "Y1 R4 W5 W1 AA6 U2" + ), + IOStandard("SSTL15")), + Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")), + Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")), + Subsignal("dq", Pins( + "Y8 AB6 W9 AA8 AB7 V7 AB8 W7", + "V4 AB2 AA5 AB3 AB5 W4 AB1 AA4" + ), + IOStandard("SSTL15"), + Misc("IN_TERM=UNTUNED_SPLIT_50")), + Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("U1"), IOStandard("SSTL15")), + Subsignal("odt", Pins("W2"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")), + Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")), + Misc("SLEW=FAST"), + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10.0 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") + self.toolchain.bitstream_commands = [ + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]", + "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" + ] + self.toolchain.additional_commands = \ + ["write_cfgmem -force -format bin -interface spix4 -size 16 " + "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] diff --git a/litex_boards/partner/platforms/nereid.py b/litex_boards/partner/platforms/nereid.py new file mode 100644 index 0000000..71d03c0 --- /dev/null +++ b/litex_boards/partner/platforms/nereid.py @@ -0,0 +1,408 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Rohit Singh +# License: BSD + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # rgb led, active-low + ("rgb_led", 0, + Subsignal("r", Pins("J26")), + Subsignal("g", Pins("H26")), + Subsignal("b", Pins("G26")), + IOStandard("LVCMOS33"), + ), + + ("clk100", 0, Pins("F22"), IOStandard("LVCMOS33")), + + ("clk150", 0, + Subsignal("p", Pins("G24"), IOStandard("TMDS_33")), + Subsignal("n", Pins("F24"), IOStandard("TMDS_33")) + ), + + # Active-high CPU reset, pulldown needed + ("cpu_reset", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLDOWN=True")), + + ("fan_pwm", 0, Pins("J25"), IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("H22")), + Subsignal("rx", Pins("K22")), + Subsignal("rts", Pins("L22")), + Subsignal("cts", Pins("L23")), + Subsignal("cbus0", Pins("K23")), + IOStandard("LVCMOS33") + ), + + ("xadc", 0, + Subsignal("adc_p", Pins("C16 A18 B17")), + Subsignal("adc_n", Pins("B16 A19 A17")), + Subsignal("v_p", Pins("N12")), + Subsignal("v_n", Pins("P11")), + ), + + ("ddram", 0, + Subsignal("a", Pins( + "AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9", + "AD8 V9 Y11 Y7 W10 Y8 Y10 W9"), + IOStandard("SSTL135")), + Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")), + Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")), + Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")), + Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")), + Subsignal("cs_n", Pins("AB12"), IOStandard("SSTL135")), + Subsignal("dm", Pins("W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"), + IOStandard("SSTL135")), + Subsignal("dq", Pins( + "V19 V16 Y17 V14 V17 V18 W14 W15", + "AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19", + "AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15", + "AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14", + "AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2", + "AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4", + "AB2 AC2 V1 W1 V2 AA3 Y1 Y2", + "V4 V3 U2 U1 U7 W3 U6 U5"), + IOStandard("SSTL135_T_DCI")), + Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"), + IOStandard("DIFF_SSTL135")), + Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"), + IOStandard("DIFF_SSTL135")), + Subsignal("clk_p", Pins("V11"), IOStandard("DIFF_SSTL135")), + Subsignal("clk_n", Pins("W11"), IOStandard("DIFF_SSTL135")), + Subsignal("cke", Pins("AA10"), IOStandard("SSTL135")), + Subsignal("odt", Pins("AD13"), IOStandard("SSTL135")), + Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")), + Misc("SLEW=FAST"), + ), + + ("ddram_dual_rank", 0, + Subsignal("a", Pins( + "AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9", + "AD8 V9 Y11 Y7 W10 Y8 Y10 W9"), + IOStandard("SSTL135")), + Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")), + Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")), + Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")), + Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")), + Subsignal("cs_n", Pins("AB12 AA12"), IOStandard("SSTL135")), + Subsignal("dm", Pins("W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"), + IOStandard("SSTL135")), + Subsignal("dq", Pins( + "V19 V16 Y17 V14 V17 V18 W14 W15", + "AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19", + "AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15", + "AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14", + "AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2", + "AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4", + "AB2 AC2 V1 W1 V2 AA3 Y1 Y2", + "V4 V3 U2 U1 U7 W3 U6 U5"), + IOStandard("SSTL135_T_DCI")), + Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"), + IOStandard("DIFF_SSTL135_T_DCI")), + Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"), + IOStandard("DIFF_SSTL135_T_DCI")), + Subsignal("clk_p", Pins("V11 V8"), IOStandard("DIFF_SSTL135")), + Subsignal("clk_n", Pins("W11 V7"), IOStandard("DIFF_SSTL135")), + Subsignal("cke", Pins("AA10 AB10"), IOStandard("SSTL135")), + Subsignal("odt", Pins("AD13 Y13"), IOStandard("SSTL135")), + Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")), + Misc("SLEW=FAST"), + ), + + ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("C23")), + Subsignal("dq", Pins("B24", "A25", "B22", "A22")), + IOStandard("LVCMOS33") + ), + + ("spiflash", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("C23")), + Subsignal("mosi", Pins("B24")), + Subsignal("miso", Pins("A25")), + Subsignal("wp", Pins("B22")), + Subsignal("hold", Pins("A22")), + IOStandard("LVCMOS33"), + ), + + ("mmc", 0, + Subsignal("cmd", Pins("H24")), + Subsignal("clk", Pins("G22")), + Subsignal("dat", Pins("F25 E25 J23 H23")), + IOStandard("LVCMOS33") + ), + + ("pcie_x1", 0, + Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("K6")), + Subsignal("clk_n", Pins("K5")), + Subsignal("rx_p", Pins("J4")), + Subsignal("rx_n", Pins("J3")), + Subsignal("tx_p", Pins("H2")), + Subsignal("tx_n", Pins("H1")) + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("K6")), + Subsignal("clk_n", Pins("K5")), + Subsignal("rx_p", Pins("J4 L4")), + Subsignal("rx_n", Pins("J3 L3")), + Subsignal("tx_p", Pins("H2 K2")), + Subsignal("tx_n", Pins("H1 K1")) + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("K6")), + Subsignal("clk_n", Pins("K5")), + Subsignal("rx_p", Pins("J4 L4 N4 R4")), + Subsignal("rx_n", Pins("J3 L3 N3 R3")), + Subsignal("tx_p", Pins("H2 K2 M2 P2")), + Subsignal("tx_n", Pins("H1 K1 M1 P1")) + ), +] + +_connectors = [ + ("HPC", { + + # FMC GTP Section + "DP0_M2C_P": "G4", + "DP0_M2C_N": "G3", + "DP1_M2C_P": "E4", + "DP1_M2C_N": "E3", + "DP2_M2C_P": "C4", + "DP2_M2C_N": "C3", + "DP3_M2C_P": "B6", + "DP3_M2C_N": "B5", + + "GBTCLK0_M2C_P": "F6", + "GBTCLK0_M2C_N": "F5", + "GBTCLK1_M2C_P": "D6", + "GBTCLK1_M2C_N": "D5", + + "DP0_C2M_P": "F2", + "DP0_C2M_N": "F1", + "DP1_C2M_P": "D2", + "DP1_C2M_N": "D1", + "DP2_C2M_P": "B2", + "DP2_C2M_N": "B1", + "DP3_C2M_P": "A4", + "DP3_C2M_N": "A3", + + # FMC LA Bank GPIOs + "LA00_P": "AA23", + "LA00_N": "AB24", + "LA01_P": "Y23", + "LA01_N": "AA24", + "LA02_P": "AD26", + "LA02_N": "AE26", + "LA03_P": "AA25", + "LA03_N": "AB25", + "LA04_P": "AD25", + "LA04_N": "AE25", + "LA05_P": "W25", + "LA05_N": "W26", + "LA06_P": "Y25", + "LA06_N": "Y26", + "LA07_P": "V23", + "LA07_N": "V24", + "LA08_P": "U26", + "LA08_N": "V26", + "LA09_P": "W20", + "LA09_N": "Y21", + "LA10_P": "V21", + "LA10_N": "W21", + "LA11_P": "L19", + "LA11_N": "L20", + "LA12_P": "M17", + "LA12_N": "L18", + "LA13_P": "K20", + "LA13_N": "J20", + "LA14_P": "J18", + "LA14_N": "J19", + "LA15_P": "U17", + "LA15_N": "T17", + "LA16_P": "T18", + "LA16_N": "T19", + "LA17_P": "E18", + "LA17_N": "D18", + "LA18_P": "F17", + "LA18_N": "E17", + "LA19_P": "H16", + "LA19_N": "G16", + "LA20_P": "K16", + "LA20_N": "K17", + "LA21_P": "D19", + "LA21_N": "D20", + "LA22_P": "C19", + "LA22_N": "B19", + "LA23_P": "C17", + "LA23_N": "C18", + "LA24_P": "D15", + "LA24_N": "D16", + "LA25_P": "F19", + "LA25_N": "E20", + "LA26_P": "J15", + "LA26_N": "J16", + "LA27_P": "G15", + "LA27_N": "F15", + "LA28_P": "G17", + "LA28_N": "F18", + "LA29_P": "E15", + "LA29_N": "E16", + "LA30_P": "H17", + "LA30_N": "H18", + "LA31_P": "G19", + "LA31_N": "F20", + "LA32_P": "H19", + "LA32_N": "G20", + "LA33_P": "L17", + "LA33_N": "K18", + + # FMC HA Bank GPIOs + "HA00_P": "P23", + "HA00_N": "N23", + "HA01_P": "N21", + "HA01_N": "N22", + "HA02_P": "AB22", + "HA02_N": "AC22", + "HA03_P": "AD23", + "HA03_N": "AD24", + "HA04_P": "N19", + "HA04_N": "M20", + "HA05_P": "R18", + "HA05_N": "P18", + "HA06_P": "P16", + "HA06_N": "N17", + "HA07_P": "R16", + "HA07_N": "R17", + "HA08_P": "U19", + "HA08_N": "U20", + "HA09_P": "N18", + "HA09_N": "M19", + "HA10_P": "T20", + "HA10_N": "R20", + "HA11_P": "P19", + "HA11_N": "P20", + "HA12_P": "T24", + "HA12_N": "T25", + "HA13_P": "U24", + "HA13_N": "U25", + "HA14_P": "R26", + "HA14_N": "P26", + "HA15_P": "P24", + "HA15_N": "N24", + "HA16_P": "R25", + "HA16_N": "P25", + "HA17_P": "M21", + "HA17_N": "M22", + "HA18_P": "N26", + "HA18_N": "M26", + "HA19_P": "K25", + "HA19_N": "K26", + "HA20_P": "M25", + "HA20_N": "L25", + "HA21_P": "M24", + "HA21_N": "L24", + "HA22_P": "T22", + "HA22_N": "T23", + "HA23_P": "U22", + "HA23_N": "V22", + + # FMC HB Bank GPIOs + "HB00_P": "E10", + "HB00_N": "D10", + "HB01_P": "F14", + "HB01_N": "F13", + "HB02_P": "H14", + "HB02_N": "G14", + "HB03_P": "J13", + "HB03_N": "H13", + "HB04_P": "B14", + "HB04_N": "A14", + "HB05_P": "B15", + "HB05_N": "A15", + "HB06_P": "C12", + "HB06_N": "C11", + "HB07_P": "G10", + "HB07_N": "G9", + "HB08_P": "E13", + "HB08_N": "E12", + "HB09_P": "D14", + "HB09_N": "D13", + "HB10_P": "C9", + "HB10_N": "B9", + "HB11_P": "A13", + "HB11_N": "A12", + "HB12_P": "B10", + "HB12_N": "A10", + "HB13_P": "B12", + "HB13_N": "B11", + "HB14_P": "F9", + "HB14_N": "F8", + "HB15_P": "E11", + "HB15_N": "D11", + "HB16_P": "D9", + "HB16_N": "D8", + "HB17_P": "G11", + "HB17_N": "F10", + "HB18_P": "G12", + "HB18_N": "F12", + "HB19_P": "A9", + "HB19_N": "A8", + "HB20_P": "J11", + "HB20_N": "J10", + "HB21_P": "H9", + "HB21_N": "H8", + + # FMC Clock and Misc signals + "CLK0_M2C_P": "Y22", + "CLK0_M2C_N": "AA22", + "CLK1_M2C_P": "AC23", + "CLK1_M2C_N": "AC24", + "CLK2_BIDIR_P": "R22", + "CLK2_BIDIR_N": "R23", + "CLK3_BIDIR_P": "R21", + "CLK3_BIDIR_N": "P21", + "CLK_DIR": "D23", + + "PG_C2M": "D26", + "PG_M2C": "E26", + "FMC_SCL": "C21", + "FMC_SDA": "B21", + "FMC_PRSNT": "B26", + } + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10.0 + + def __init__(self, toolchain="vivado", programmer="xc3sprog"): + XilinxPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors, + toolchain=toolchain) + + self.add_platform_command(""" +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +""") + self.toolchain.bitstream_commands = [ + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]", + "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" + ] + self.toolchain.additional_commands = \ + ["write_cfgmem -force -format bin -interface spix4 -size 16 " + "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + self.programmer = programmer + + def create_programmer(self): + if self.programmer == "vivado": + return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") + else: + raise ValueError("{} programmer is not supported".format(self.programmer)) + diff --git a/litex_boards/partner/platforms/tagus.py b/litex_boards/partner/platforms/tagus.py new file mode 100644 index 0000000..bcd99e3 --- /dev/null +++ b/litex_boards/partner/platforms/tagus.py @@ -0,0 +1,169 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Rohit Singh +# License: BSD + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # clk / rst + ("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")), + ("rst", 0, Pins("P17"), IOStandard("LVCMOS33")), + + # leds (only a single rgb led, aliased here also) + ("user_led", 0, Pins("W21"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("W22"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("AA20"), IOStandard("LVCMOS33")), + + ("rgb_led", 0, + Subsignal("r", Pins("W21")), + Subsignal("g", Pins("W22")), + Subsignal("b", Pins("AA20")), + IOStandard("LVCMOS33"), + ), + + ("serial", 0, + Subsignal("tx", Pins("R14")), + Subsignal("rx", Pins("P14")), + Subsignal("rts", Pins("R18")), + Subsignal("cts", Pins("T18")), + Subsignal("cbus0", Pins("N17")), + IOStandard("LVCMOS33") + ), + + # flash + ("flash", 0, + Subsignal("cs_n", Pins("T19")), + Subsignal("mosi", Pins("P22")), + Subsignal("miso", Pins("R22")), + Subsignal("vvp", Pins("P21")), + Subsignal("hold", Pins("R21")), + IOStandard("LVCMOS33") + ), + + ("flash4x", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("T19")), + Subsignal("dq", Pins("P22", "R22", "P21", "R21")), + IOStandard("LVCMOS33") + ), + + # tpm + ("tpm", 0, + Subsignal("clk", Pins("Y18")), + Subsignal("rst_n", Pins("AA19")), + Subsignal("cs_n", Pins("Y19")), + Subsignal("mosi", Pins("V18")), + Subsignal("miso", Pins("V19")), + IOStandard("LVCMOS33"), + ), + + # pcie + ("pcie_x1", 0, + Subsignal("rst_n", Pins("W20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("F6")), + Subsignal("clk_n", Pins("E6")), + Subsignal("rx_p", Pins("B8")), + Subsignal("rx_n", Pins("A8")), + Subsignal("tx_p", Pins("B4")), + Subsignal("tx_n", Pins("A4")) + ), + + # dram + ("ddram", 0, + Subsignal("a", Pins( + "U6 T5 Y6 T6 V2 T4 Y2 R2", + "Y1 R4 W5 W1 AA6 U2" + ), + IOStandard("SSTL15")), + Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")), + Subsignal("dm", Pins("Y7 K1"), IOStandard("SSTL15")), + Subsignal("dq", Pins( + "Y8 AB6 W9 AA8 AB7 V7 AB8 W7", + "H4 G2 J5 H2 H5 G4 J1 G3" + ), + IOStandard("SSTL15"), + Misc("IN_TERM=UNTUNED_SPLIT_50")), + Subsignal("dqs_p", Pins("V9 K2"), IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("V8 J2"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("U1"), IOStandard("SSTL15")), + Subsignal("odt", Pins("W2"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")), + Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")), + Misc("SLEW=FAST"), + ), + + # sdcard + ("sdcard", 0, + Subsignal("data", Pins("P19 Y22 Y21 T21")), + Subsignal("cmd", Pins("U21")), + Subsignal("clk", Pins("R19")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + + # sfp0 + ("sfp_tx", 0, + Subsignal("p", Pins("B6")), + Subsignal("n", Pins("A6")) + ), + ("sfp_rx", 0, + Subsignal("p", Pins("B10")), + Subsignal("n", Pins("A10")) + ), + ("sfp_tx_disable_n", 0, Pins("V22"), IOStandard("LVCMOS33")), + ("sfp_rx_los", 0, Pins("AB21"), IOStandard("LVCMOS33")), + + # sfp1 + ("sfp_tx", 1, + Subsignal("p", Pins("D7")), + Subsignal("n", Pins("C7")) + ), + ("sfp_rx", 1, + Subsignal("p", Pins("D9")), + Subsignal("n", Pins("C9")) + ), + ("sfp_tx_disable_n", 1, Pins("P15"), IOStandard("LVCMOS33")), + ("sfp_rx_los", 1, Pins("R17"), IOStandard("LVCMOS33")), +] + + +# TODO: Add complete LPC IOs +_connectors = [ + ("LPC", { + # FMC GTP Section + "DP0_M2C_P": "D11", + "DP0_M2C_N": "C11", + + "GBTCLK0_M2C_P": "F10", + "GBTCLK0_M2C_N": "E10", + + "DP0_C2M_P": "D5", + "DP0_C2M_N": "C5", + } + ) +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10.0 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") + self.toolchain.bitstream_commands = [ + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]", + "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" + ] + self.toolchain.additional_commands = \ + ["write_cfgmem -force -format bin -interface spix4 -size 16 " + "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] diff --git a/litex_boards/partner/targets/__init__.py b/litex_boards/partner/targets/__init__.py index 55db527..5f0efc9 100644 --- a/litex_boards/partner/targets/__init__.py +++ b/litex_boards/partner/targets/__init__.py @@ -1,3 +1,6 @@ +from litex_boards.partner.targets import aller +from litex_boards.partner.targets import nereid from litex_boards.partner.targets import netv2 +from litex_boards.partner.targets import tagus from litex_boards.partner.targets import trellisboard from litex_boards.partner.targets import ulx3s diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py new file mode 100755 index 0000000..bab9af7 --- /dev/null +++ b/litex_boards/partner/targets/aller.py @@ -0,0 +1,209 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Rohit Singh +# License: BSD + +import sys + +from migen import * + +from litex.build.generic_platform import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * +from litex.soc.cores.clock import * +from litex.soc.cores import dna, xadc +from litex.soc.cores.uart import * +from litex.soc.integration.cpu_interface import get_csr_header + +from litedram.modules import MT41J128M16 +from litedram.phy import s7ddrphy + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.core import LitePCIeEndpoint, LitePCIeMSI +from litepcie.frontend.dma import LitePCIeDMA +from litepcie.frontend.wishbone import LitePCIeWishboneBridge + +from litex_boards.platforms import aller + +# CRG ---------------------------------------------------------------------------------------------- + +class CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + self.clock_domains.cd_clk200 = ClockDomain() + + clk100 = platform.request("clk100") + + self.submodules.pll = pll = S7PLL() + pll.register_clkin(clk100, 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + +# AllerSoC ------------------------------------------------------------------------------------------ + +class AllerSoC(SoCSDRAM): + SoCSDRAM.mem_map["csr"] = 0x00000000 + SoCSDRAM.mem_map["rom"] = 0x20000000 + + def __init__(self, platform, with_pcie_uart=True): + sys_clk_freq = int(100e6) + + # soc sdram + # ------------------------------------------------------------------------------------------ + SoCSDRAM.__init__(self, platform, sys_clk_freq, + csr_data_width=32, + integrated_rom_size=0x10000, + integrated_sram_size=0x10000, + integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests + ident="Aller LiteX Test SoC", ident_version=True, + with_uart=not with_pcie_uart) + + # crg + # ------------------------------------------------------------------------------------------ + self.submodules.crg = CRG(platform, sys_clk_freq) + self.add_csr("crg") + + # dna + # ------------------------------------------------------------------------------------------ + self.submodules.dna = dna.DNA() + self.add_csr("dna") + + # xadc + # ------------------------------------------------------------------------------------------ + self.submodules.xadc = xadc.XADC() + self.add_csr("xadc") + + # sdram + # ------------------------------------------------------------------------------------------ + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.A7DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq, + iodelay_clk_freq=200e6) + sdram_module = MT41J128M16(sys_clk_freq, "1:4") + self.register_sdram(self.ddrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + self.add_csr("ddrphy") + + # pcie + # ------------------------------------------------------------------------------------------ + # pcie phy + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) + self.pcie_phy.cd_pcie.clk.attr.add("keep") + platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.pcie_phy.cd_pcie.clk) + self.add_csr("pcie_phy") + + # pcie endpoint + self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) + + # pcie wishbone bridge + self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base) + self.add_wb_master(self.pcie_wishbone.wishbone) + + # pcie dma + self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, + with_buffering=True, buffering_depth=1024, with_loopback=True) + self.add_csr("pcie_dma") + + # pcie msi + self.submodules.pcie_msi = LitePCIeMSI() + self.add_csr("pcie_msi") + self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) + self.msis = { + "DMA_WRITER": self.pcie_dma.writer.irq, + "DMA_READER": self.pcie_dma.reader.irq + } + for i, (k, v) in enumerate(sorted(self.msis.items())): + self.comb += self.pcie_msi.irqs[i].eq(v) + self.add_constant(k + "_INTERRUPT", i) + + # pcie_uart + # ------------------------------------------------------------------------------------------ + if with_pcie_uart: + class PCIeUART(Module, AutoCSR): + def __init__(self, uart): + self.rx_valid = CSRStatus() + self.rx_ready = CSR() + self.rx_data = CSRStatus(8) + + self.tx_valid = CSR() + self.tx_ready = CSRStatus() + self.tx_data = CSRStorage(8) + + # # # + + # cpu to pcie + self.comb += [ + self.rx_valid.status.eq(uart.sink.valid), + uart.sink.ready.eq(self.rx_ready.re), + self.rx_data.status.eq(uart.sink.data), + ] + + # pcie to cpu + self.sync += [ + If(self.tx_valid.re, + uart.source.valid.eq(1) + ).Elif(uart.source.ready, + uart.source.valid.eq(0) + ) + ] + self.comb += [ + self.tx_ready.status.eq(~uart.source.valid), + uart.source.data.eq(self.tx_data.storage) + ] + + uart_interface = RS232PHYInterface() + self.submodules.uart = UART(uart_interface) + self.add_csr("uart") + self.add_interrupt("uart") + self.submodules.pcie_uart = PCIeUART(uart_interface) + self.add_csr("pcie_uart") + + # leds + # ------------------------------------------------------------------------------------------ + # led blinking (sys) + sys_counter = Signal(32) + self.sync.sys += sys_counter.eq(sys_counter + 1) + + pcie_counter = Signal(32) + self.sync.pcie += pcie_counter.eq(pcie_counter + 1) + + self.comb += [ + platform.request("user_led", 0).eq(~self.pcie_phy._lnk_up.status), + platform.request("user_led", 1).eq(~pcie_counter[26]), + platform.request("user_led", 2).eq(~sys_counter[26]), + ] + + def generate_software_header(self, filename): + csr_header = get_csr_header(self.get_csr_regions(), + self.get_constants(), + with_access_functions=False, + with_shadow_base=False) + tools.write_to_file(filename, csr_header) + + +# Build -------------------------------------------------------------------------------------------- + +def main(): + platform = aller.Platform() + soc = AllerSoC(platform) + builder = Builder(soc, output_dir="../build/aller", csr_csv="../build/aller/csr.csv", + compile_gateware=not "no-compile" in sys.argv[1:]) + vns = builder.build(build_name="aller") + soc.generate_software_header("../software/kernel/csr.h") + + +if __name__ == "__main__": + main() diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py new file mode 100755 index 0000000..1099bd7 --- /dev/null +++ b/litex_boards/partner/targets/nereid.py @@ -0,0 +1,224 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Rohit Singh +# License: BSD + +import sys + +from migen import * + +from litex.build.generic_platform import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * +from litex.soc.cores.clock import * +from litex.soc.cores import dna, xadc +from litex.soc.cores.uart import * +from litex.soc.integration.cpu_interface import get_csr_header + +from litedram.modules import SDRAMModule +from litedram.modules import _TechnologyTimings, _SpeedgradeTimings +from litedram.phy import s7ddrphy + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.core import LitePCIeEndpoint, LitePCIeMSI +from litepcie.frontend.dma import LitePCIeDMA +from litepcie.frontend.wishbone import LitePCIeWishboneBridge + +from litex_boards.platforms import nereid + +# sdram module +# -------------------------------------------------------------------------------------------------- + +class MT8KTF51264(SDRAMModule): + memtype = "DDR3" + # geometry + nbanks = 8 + nrows = 16384 + ncols = 1024 + # timings + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10)) + speedgrade_timings = { + "800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=260, tFAW=(None, 50), tRAS=None), + "1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRAS=None), + "1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRAS=None), + } + speedgrade_timings["default"] = speedgrade_timings["1333"] + +# CRG ---------------------------------------------------------------------------------------------- + +class CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_clk200 = ClockDomain() + + clk100 = platform.request("clk100") + + self.submodules.pll = pll = S7PLL() + pll.register_clkin(clk100, 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_clk200, 200e6) + self.comb += pll.reset.eq(platform.request("cpu_reset")) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + +# NereidSoC ------------------------------------------------------------------------------------------ + +class NereidSoC(SoCSDRAM): + SoCSDRAM.mem_map["csr"] = 0x00000000 + SoCSDRAM.mem_map["rom"] = 0x20000000 + + def __init__(self, platform, with_pcie_uart=True): + sys_clk_freq = int(100e6) + + # soc sdram + # ------------------------------------------------------------------------------------------ + SoCSDRAM.__init__(self, platform, sys_clk_freq, + csr_data_width=32, + integrated_rom_size=0x10000, + integrated_sram_size=0x10000, + integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests + ident="Nereid LiteX Test SoC", ident_version=True, + with_uart=not with_pcie_uart) + + # crg + # ------------------------------------------------------------------------------------------ + self.submodules.crg = CRG(platform, sys_clk_freq) + self.add_csr("crg") + + # dna + # ------------------------------------------------------------------------------------------ + self.submodules.dna = dna.DNA() + self.add_csr("dna") + + # xadc + # ------------------------------------------------------------------------------------------ + self.submodules.xadc = xadc.XADC() + self.add_csr("xadc") + + # sdram + # ------------------------------------------------------------------------------------------ + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.K7DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq, + iodelay_clk_freq=200e6) + sdram_module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800") + self.register_sdram(self.ddrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + self.add_csr("ddrphy") + + # pcie + # ------------------------------------------------------------------------------------------ + # pcie phy + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) + self.pcie_phy.cd_pcie.clk.attr.add("keep") + platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.pcie_phy.cd_pcie.clk) + self.add_csr("pcie_phy") + + # pcie endpoint + self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) + + # pcie wishbone bridge + self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base) + self.add_wb_master(self.pcie_wishbone.wishbone) + + # pcie dma + self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, + with_buffering=True, buffering_depth=1024, with_loopback=True) + self.add_csr("pcie_dma") + + # pcie msi + self.submodules.pcie_msi = LitePCIeMSI() + self.add_csr("pcie_msi") + self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) + self.msis = { + "DMA_WRITER": self.pcie_dma.writer.irq, + "DMA_READER": self.pcie_dma.reader.irq + } + for i, (k, v) in enumerate(sorted(self.msis.items())): + self.comb += self.pcie_msi.irqs[i].eq(v) + self.add_constant(k + "_INTERRUPT", i) + + # pcie_uart + # ------------------------------------------------------------------------------------------ + if with_pcie_uart: + class PCIeUART(Module, AutoCSR): + def __init__(self, uart): + self.rx_valid = CSRStatus() + self.rx_ready = CSR() + self.rx_data = CSRStatus(8) + + self.tx_valid = CSR() + self.tx_ready = CSRStatus() + self.tx_data = CSRStorage(8) + + # # # + + # cpu to pcie + self.comb += [ + self.rx_valid.status.eq(uart.sink.valid), + uart.sink.ready.eq(self.rx_ready.re), + self.rx_data.status.eq(uart.sink.data), + ] + + # pcie to cpu + self.sync += [ + If(self.tx_valid.re, + uart.source.valid.eq(1) + ).Elif(uart.source.ready, + uart.source.valid.eq(0) + ) + ] + self.comb += [ + self.tx_ready.status.eq(~uart.source.valid), + uart.source.data.eq(self.tx_data.storage) + ] + + uart_interface = RS232PHYInterface() + self.submodules.uart = UART(uart_interface) + self.add_csr("uart") + self.add_interrupt("uart") + self.submodules.pcie_uart = PCIeUART(uart_interface) + self.add_csr("pcie_uart") + + # leds + # ------------------------------------------------------------------------------------------ + # led blinking (sys) + sys_counter = Signal(32) + self.sync.sys += sys_counter.eq(sys_counter + 1) + rgb = platform.request("rgb_led") + self.comb += [ + rgb.r.eq(1), + rgb.g.eq(sys_counter[26]), + rgb.b.eq(1), + ] + + def generate_software_header(self, filename): + csr_header = get_csr_header(self.get_csr_regions(), + self.get_constants(), + with_access_functions=False, + with_shadow_base=False) + tools.write_to_file(filename, csr_header) + + +# Build -------------------------------------------------------------------------------------------- + +def main(): + platform = nereid.Platform() + soc = NereidSoC(platform) + builder = Builder(soc, output_dir="../build/nereid", csr_csv="../build/nereid/csr.csv", + compile_gateware=not "no-compile" in sys.argv[1:]) + vns = builder.build(build_name="nereid") + soc.generate_software_header("../software/kernel/csr.h") + + +if __name__ == "__main__": + main() diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py new file mode 100755 index 0000000..0ed1ff4 --- /dev/null +++ b/litex_boards/partner/targets/tagus.py @@ -0,0 +1,206 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Rohit Singh +# License: BSD + +import sys + +from migen import * + +from litex.build.generic_platform import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * +from litex.soc.cores.clock import * +from litex.soc.cores import dna, xadc +from litex.soc.cores.uart import * +from litex.soc.integration.cpu_interface import get_csr_header + +from litedram.modules import MT41J128M16 +from litedram.phy import s7ddrphy + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.core import LitePCIeEndpoint, LitePCIeMSI +from litepcie.frontend.dma import LitePCIeDMA +from litepcie.frontend.wishbone import LitePCIeWishboneBridge + +from litex_boards.platforms import tagus + +# CRG ---------------------------------------------------------------------------------------------- + +class CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + self.clock_domains.cd_clk200 = ClockDomain() + + clk100 = platform.request("clk100") + + self.submodules.pll = pll = S7PLL() + pll.register_clkin(clk100, 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + self.comb += pll.reset.eq(platform.request("rst")) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + +# NereidSoC ------------------------------------------------------------------------------------------ + +class TagusSoC(SoCSDRAM): + SoCSDRAM.mem_map["csr"] = 0x00000000 + SoCSDRAM.mem_map["rom"] = 0x20000000 + + def __init__(self, platform, with_pcie_uart=True): + sys_clk_freq = int(100e6) + + # soc sdram + # ------------------------------------------------------------------------------------------ + SoCSDRAM.__init__(self, platform, sys_clk_freq, + csr_data_width=32, + integrated_rom_size=0x10000, + integrated_sram_size=0x10000, + integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests + ident="Tagus LiteX Test SoC", ident_version=True, + with_uart=not with_pcie_uart) + + # crg + # ------------------------------------------------------------------------------------------ + self.submodules.crg = CRG(platform, sys_clk_freq) + self.add_csr("crg") + + # dna + # ------------------------------------------------------------------------------------------ + self.submodules.dna = dna.DNA() + self.add_csr("dna") + + # xadc + # ------------------------------------------------------------------------------------------ + self.submodules.xadc = xadc.XADC() + self.add_csr("xadc") + + # sdram + # ------------------------------------------------------------------------------------------ + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.A7DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq, + iodelay_clk_freq=200e6) + sdram_module = MT41J128M16(sys_clk_freq, "1:4") + self.register_sdram(self.ddrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + self.add_csr("ddrphy") + + # pcie + # ------------------------------------------------------------------------------------------ + # pcie phy + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) + self.pcie_phy.cd_pcie.clk.attr.add("keep") + platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.pcie_phy.cd_pcie.clk) + self.add_csr("pcie_phy") + + # pcie endpoint + self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) + + # pcie wishbone bridge + self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base) + self.add_wb_master(self.pcie_wishbone.wishbone) + + # pcie dma + self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, + with_buffering=True, buffering_depth=1024, with_loopback=True) + self.add_csr("pcie_dma") + + # pcie msi + self.submodules.pcie_msi = LitePCIeMSI() + self.add_csr("pcie_msi") + self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) + self.msis = { + "DMA_WRITER": self.pcie_dma.writer.irq, + "DMA_READER": self.pcie_dma.reader.irq + } + for i, (k, v) in enumerate(sorted(self.msis.items())): + self.comb += self.pcie_msi.irqs[i].eq(v) + self.add_constant(k + "_INTERRUPT", i) + + # pcie_uart + # ------------------------------------------------------------------------------------------ + if with_pcie_uart: + class PCIeUART(Module, AutoCSR): + def __init__(self, uart): + self.rx_valid = CSRStatus() + self.rx_ready = CSR() + self.rx_data = CSRStatus(8) + + self.tx_valid = CSR() + self.tx_ready = CSRStatus() + self.tx_data = CSRStorage(8) + + # # # + + # cpu to pcie + self.comb += [ + self.rx_valid.status.eq(uart.sink.valid), + uart.sink.ready.eq(self.rx_ready.re), + self.rx_data.status.eq(uart.sink.data), + ] + + # pcie to cpu + self.sync += [ + If(self.tx_valid.re, + uart.source.valid.eq(1) + ).Elif(uart.source.ready, + uart.source.valid.eq(0) + ) + ] + self.comb += [ + self.tx_ready.status.eq(~uart.source.valid), + uart.source.data.eq(self.tx_data.storage) + ] + + uart_interface = RS232PHYInterface() + self.submodules.uart = UART(uart_interface) + self.add_csr("uart") + self.add_interrupt("uart") + self.submodules.pcie_uart = PCIeUART(uart_interface) + self.add_csr("pcie_uart") + + # leds + # ------------------------------------------------------------------------------------------ + # led blinking (sys) + sys_counter = Signal(32) + self.sync.sys += sys_counter.eq(sys_counter + 1) + self.comb += [ + platform.request("user_led", 0).eq(1), + platform.request("user_led", 1).eq(sys_counter[26]), + platform.request("user_led", 2).eq(1), + ] + + def generate_software_header(self, filename): + csr_header = get_csr_header(self.get_csr_regions(), + self.get_constants(), + with_access_functions=False, + with_shadow_base=False) + tools.write_to_file(filename, csr_header) + + +# Build -------------------------------------------------------------------------------------------- + +def main(): + platform = tagus.Platform() + soc = TagusSoC(platform) + builder = Builder(soc, output_dir="../build/tagus", csr_csv="../build/tagus/csr.csv", + compile_gateware=not "no-compile" in sys.argv[1:]) + vns = builder.build(build_name="tagus") + soc.generate_software_header("../software/kernel/csr.h") + + +if __name__ == "__main__": + main() From e704014b3643129e39e2b88fadc02a2581c2696b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 1 Sep 2019 11:43:21 +0200 Subject: [PATCH 2/8] targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them. --- litex_boards/community/targets/__init__.py | 10 +++++----- litex_boards/official/targets/__init__.py | 20 ++++++++++---------- litex_boards/partner/targets/__init__.py | 6 +++--- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/litex_boards/community/targets/__init__.py b/litex_boards/community/targets/__init__.py index 1f148f7..a1fcf29 100644 --- a/litex_boards/community/targets/__init__.py +++ b/litex_boards/community/targets/__init__.py @@ -1,5 +1,5 @@ -from litex_boards.community.targets import ac701 -from litex_boards.community.targets import de10lite -from litex_boards.community.targets import de1soc -from litex_boards.community.targets import de2_115 -from litex_boards.community.targets import ecp5_evn +#from litex_boards.community.targets import ac701 +#from litex_boards.community.targets import de10lite +#from litex_boards.community.targets import de1soc +#from litex_boards.community.targets import de2_115 +#from litex_boards.community.targets import ecp5_evn diff --git a/litex_boards/official/targets/__init__.py b/litex_boards/official/targets/__init__.py index a0a1415..985dbcd 100644 --- a/litex_boards/official/targets/__init__.py +++ b/litex_boards/official/targets/__init__.py @@ -1,10 +1,10 @@ -from litex_boards.official.targets import arty -from litex_boards.official.targets import de0nano -from litex_boards.official.targets import genesys2 -from litex_boards.official.targets import kc705 -from litex_boards.official.targets import kcu105 -from litex_boards.official.targets import minispartan6 -from litex_boards.official.targets import nexys4ddr -from litex_boards.official.targets import nexys_video -from litex_boards.official.targets import simple -from litex_boards.official.targets import versa_ecp5 +#from litex_boards.official.targets import arty +#from litex_boards.official.targets import de0nano +#from litex_boards.official.targets import genesys2 +#from litex_boards.official.targets import kc705 +#from litex_boards.official.targets import kcu105 +#from litex_boards.official.targets import minispartan6 +#from litex_boards.official.targets import nexys4ddr +#from litex_boards.official.targets import nexys_video +#from litex_boards.official.targets import simple +#from litex_boards.official.targets import versa_ecp5 diff --git a/litex_boards/partner/targets/__init__.py b/litex_boards/partner/targets/__init__.py index 55db527..4195a64 100644 --- a/litex_boards/partner/targets/__init__.py +++ b/litex_boards/partner/targets/__init__.py @@ -1,3 +1,3 @@ -from litex_boards.partner.targets import netv2 -from litex_boards.partner.targets import trellisboard -from litex_boards.partner.targets import ulx3s +#from litex_boards.partner.targets import netv2 +#from litex_boards.partner.targets import trellisboard +#from litex_boards.partner.targets import ulx3s From bdbd2ec1c0cee47237ab722d080e3bfac128380f Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Mon, 2 Sep 2019 10:35:37 +0800 Subject: [PATCH 3/8] partner: add fomu target This adds the Fomu target back in. The default BaseSoC supports various USB methods, and will be updated as more become available. The debug bridge may optionally be added. Signed-off-by: Sean Cross --- litex_boards/partner/targets/fomu.py | 246 +++++++++++++++++++++++++++ 1 file changed, 246 insertions(+) create mode 100644 litex_boards/partner/targets/fomu.py diff --git a/litex_boards/partner/targets/fomu.py b/litex_boards/partner/targets/fomu.py new file mode 100644 index 0000000..903cb5c --- /dev/null +++ b/litex_boards/partner/targets/fomu.py @@ -0,0 +1,246 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018 David Shah +# License: BSD + +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.soc.cores import up5kspram +from litex.soc.integration import SoCCore +from litex.soc.integration.builder import Builder, builder_argdict, builder_args +from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args + +from valentyusb.usbcore import io as usbio +from valentyusb.usbcore.cpu import dummyusb, epfifo + +import os, shutil, subprocess + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform): + clk48_raw = platform.request("clk48") + clk12 = Signal() + + reset_delay = Signal(12, reset=4095) + self.clock_domains.cd_por = ClockDomain() + self.reset = Signal() + + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + + platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) + platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) + platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) + platform.add_period_constraint(clk48_raw, 1e9/48e6) + + # POR reset logic- POR generated from sys clk, POR logic feeds sys clk + # reset. + self.comb += [ + self.cd_por.clk.eq(self.cd_sys.clk), + self.cd_sys.rst.eq(reset_delay != 0), + self.cd_usb_12.rst.eq(reset_delay != 0), + ] + + # POR reset logic- POR generated from sys clk, POR logic feeds sys clk + # reset. + self.comb += [ + self.cd_usb_48.rst.eq(reset_delay != 0), + ] + + self.comb += self.cd_usb_48.clk.eq(clk48_raw) + + self.specials += Instance( + "SB_PLL40_CORE", + # Parameters + p_DIVR = 0, + p_DIVF = 15, + p_DIVQ = 5, + p_FILTER_RANGE = 1, + p_FEEDBACK_PATH = "SIMPLE", + p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED", + p_FDA_FEEDBACK = 15, + p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED", + p_FDA_RELATIVE = 0, + p_SHIFTREG_DIV_MODE = 1, + p_PLLOUT_SELECT = "GENCLK_HALF", + p_ENABLE_ICEGATE = 0, + # IO + i_REFERENCECLK = clk48_raw, + o_PLLOUTCORE = clk12, + # o_PLLOUTGLOBAL = clk12, + #i_EXTFEEDBACK, + #i_DYNAMICDELAY, + #o_LOCK, + i_BYPASS = 0, + i_RESETB = 1, + #i_LATCHINPUTVALUE, + #o_SDO, + #i_SDI, + ) + + self.comb += self.cd_sys.clk.eq(clk12) + self.comb += self.cd_usb_12.clk.eq(clk12) + + self.sync.por += \ + If(reset_delay != 0, + reset_delay.eq(reset_delay - 1) + ) + self.specials += AsyncResetSynchronizer(self.cd_por, self.reset) + + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + """A SoC on Fomu, optionally with a softcore CPU""" + + # Create a default CSR map to prevent values from getting reassigned. + # This increases consistency across litex versions. + SoCCore.csr_map = { + "ctrl": 0, # provided by default (optional) + "crg": 1, # user + "uart_phy": 2, # provided by default (optional) + "uart": 3, # provided by default (optional) + "identifier_mem": 4, # provided by default (optional) + "timer0": 5, # provided by default (optional) + "cpu_or_bridge": 8, + "usb": 9, + "picorvspi": 10, + "touch": 11, + "reboot": 12, + "rgb": 13, + "version": 14, + } + + # Statically-define the memory map, to prevent it from shifting across + # various litex versions. + SoCCore.mem_map = { + "rom": 0x00000000, # (default shadow @0x80000000) + "sram": 0x10000000, # (default shadow @0xa0000000) + "spiflash": 0x20000000, # (default shadow @0xa0000000) + "main_ram": 0x40000000, # (default shadow @0xc0000000) + "csr": 0x60000000, # (default shadow @0xe0000000) + } + + interrupt_map = { + "usb": 3, + } + interrupt_map.update(SoCCore.interrupt_map) + + def __init__(self, board, + pnr_placer=None, pnr_seed=0, usb_core="dummyusb", usb_bridge=False, + **kwargs): + """Create a basic SoC for Fomu. + + Create a basic SoC for Fomu, including a 48 MHz and 12 MHz clock + domain called `usb_48` and `usb_12`. The `sys` frequency will + run at 12 MHz. + + The USB core will optionally have a bridge to the Wishbone bus. + + Args: + board (str): Which Fomu board to build for: pvt, evt, or hacker + pnr_placer (str): Which placer to use in nextpnr + pnr_seed (int): Which seed to use in nextpnr + usb_core (str): The name of the USB core to use, if any: dummyusb, epfifo + usb_bridge (bool): Whether to include a USB-to-Wishbone bridge + Raises: + ValueError: If either the `usb_core` or `board` are unrecognized + Returns: + Newly-constructed SoC + """ + if board == "pvt": + from litex_boards.partner.platforms.fomu_pvt import Platform + elif board == "hacker": + from litex_boards.partner.platforms.fomu_hacker import Platform + elif board == "evt": + from litex_boards.partner.platforms.fomu_evt import Platform + else: + raise ValueError("unrecognized fomu board: {}".format(board)) + platform = Platform() + + clk_freq = int(12e6) + + SoCCore.__init__(self, platform, clk_freq, + cpu_type=None, + cpu_variant=None, + integrated_sram_size=0, + with_uart=False, + with_ctrl=False, + **kwargs) + + self.submodules.crg = _CRG(platform) + + # UP5K has single port RAM, which is a dedicated 128 kilobyte block. + # Use this as CPU RAM. + spram_size = 128*1024 + self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size) + self.register_mem("sram", 0x10000000, self.spram.bus, spram_size) + + if usb_core is not None: + # Add USB pads. We use DummyUsb, which simply enumerates as a USB + # device. Then all interaction is done via the wishbone bridge. + usb_pads = platform.request("usb") + usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup) + if usb_core == "dummyusb": + self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_bridge) + elif usb_core == "epfifo": + self.submodules.usb = epfifo.PerEndpointFifo(usb_iobuf, debug=usb_bridge) + else: + raise ValueError("unrecognized usb_core: {}".args(usb_core)) + if usb_bridge: + self.add_wb_master(self.usb.debug_bridge.wishbone) + + # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. + # "-reult" adds an additional LUT pass to pack more stuff in, and + # "-dffe_min_ce_use 4" flag prevents Yosys from generating a + # Clock Enable signal for a LUT that has fewer than 4 flip-flops. + # This increases density, and lets us use the FPGA more efficiently. + platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4" + + # Allow us to set the nextpnr seed, because some values don't meet timing. + platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed) + + # Different placers can improve packing efficiency, however not all placers + # are enabled on all builds of nextpnr-ice40. Let the user override which + # placer they want to use. + if pnr_placer is not None: + platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(pnr_placer) + + +# Build -------------------------------------------------------------------------------------------- + +def add_dfu_suffix(fn): + fn_base, _ext = os.path.splitext(fn) + fn_dfu = fn_base + '.dfu' + shutil.copyfile(fn, fn_dfu) + subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu]) + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on Fomu") + parser.add_argument( + "--board", choices=["evt", "pvt", "hacker"], required=True, + help="build for a particular hardware board" + ) + parser.add_argument( + "--seed", default=0, help="seed to use in nextpnr" + ) + parser.add_argument( + "--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr" + ) + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed, + debug=True, **soc_core_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + +if __name__ == "__main__": + main() From d78965ffb24164dd5c8775038700333a6a06cf22 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Sep 2019 11:23:43 +0200 Subject: [PATCH 4/8] partner/targets/fomu fix copyright & mode --- litex_boards/partner/targets/fomu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) mode change 100644 => 100755 litex_boards/partner/targets/fomu.py diff --git a/litex_boards/partner/targets/fomu.py b/litex_boards/partner/targets/fomu.py old mode 100644 new mode 100755 index 903cb5c..302ec08 --- a/litex_boards/partner/targets/fomu.py +++ b/litex_boards/partner/targets/fomu.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2019 Sean Cross # This file is Copyright (c) 2018 David Shah # License: BSD From ec5540454b05bea43fea309dbf689be79b06ddea Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Sep 2019 11:43:13 +0200 Subject: [PATCH 5/8] partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic --- litex_boards/partner/platforms/aller.py | 2 +- litex_boards/partner/platforms/nereid.py | 2 +- litex_boards/partner/platforms/tagus.py | 2 +- litex_boards/partner/targets/aller.py | 27 +++++++------------ litex_boards/partner/targets/nereid.py | 34 +++++++++--------------- litex_boards/partner/targets/tagus.py | 28 +++++++------------ 6 files changed, 34 insertions(+), 61 deletions(-) diff --git a/litex_boards/partner/platforms/aller.py b/litex_boards/partner/platforms/aller.py index 112d184..9315044 100644 --- a/litex_boards/partner/platforms/aller.py +++ b/litex_boards/partner/platforms/aller.py @@ -1,5 +1,5 @@ -# This file is Copyright (c) 2018-2019 Florent Kermarrec # This file is Copyright (c) 2018-2019 Rohit Singh +# This file is Copyright (c) 2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/partner/platforms/nereid.py b/litex_boards/partner/platforms/nereid.py index 71d03c0..53299f6 100644 --- a/litex_boards/partner/platforms/nereid.py +++ b/litex_boards/partner/platforms/nereid.py @@ -1,5 +1,5 @@ -# This file is Copyright (c) 2018-2019 Florent Kermarrec # This file is Copyright (c) 2018-2019 Rohit Singh +# This file is Copyright (c) 2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/partner/platforms/tagus.py b/litex_boards/partner/platforms/tagus.py index bcd99e3..5e0e658 100644 --- a/litex_boards/partner/platforms/tagus.py +++ b/litex_boards/partner/platforms/tagus.py @@ -1,5 +1,5 @@ -# This file is Copyright (c) 2018-2019 Florent Kermarrec # This file is Copyright (c) 2018-2019 Rohit Singh +# This file is Copyright (c) 2018 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py index bab9af7..ad677bc 100755 --- a/litex_boards/partner/targets/aller.py +++ b/litex_boards/partner/targets/aller.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 -# This file is Copyright (c) 2018-2019 Florent Kermarrec # This file is Copyright (c) 2018-2019 Rohit Singh +# This file is Copyright (c) 2019 Florent Kermarrec # License: BSD import sys @@ -55,9 +55,6 @@ class AllerSoC(SoCSDRAM): def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) - - # soc sdram - # ------------------------------------------------------------------------------------------ SoCSDRAM.__init__(self, platform, sys_clk_freq, csr_data_width=32, integrated_rom_size=0x10000, @@ -66,23 +63,19 @@ class AllerSoC(SoCSDRAM): ident="Aller LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) - # crg - # ------------------------------------------------------------------------------------------ + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # dna - # ------------------------------------------------------------------------------------------ + # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") - # xadc - # ------------------------------------------------------------------------------------------ + # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") - # sdram - # ------------------------------------------------------------------------------------------ + # SDRAM ------------------------------------------------------------------------------------ if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), @@ -94,8 +87,7 @@ class AllerSoC(SoCSDRAM): sdram_module.timing_settings) self.add_csr("ddrphy") - # pcie - # ------------------------------------------------------------------------------------------ + # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") @@ -109,7 +101,8 @@ class AllerSoC(SoCSDRAM): self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge - self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base) + self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, + lambda a: 1, shadow_base=self.shadow_base) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma @@ -130,7 +123,6 @@ class AllerSoC(SoCSDRAM): self.add_constant(k + "_INTERRUPT", i) # pcie_uart - # ------------------------------------------------------------------------------------------ if with_pcie_uart: class PCIeUART(Module, AutoCSR): def __init__(self, uart): @@ -171,8 +163,7 @@ class AllerSoC(SoCSDRAM): self.submodules.pcie_uart = PCIeUART(uart_interface) self.add_csr("pcie_uart") - # leds - # ------------------------------------------------------------------------------------------ + # Leds ------------------------------------------------------------------------------------- # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index 1099bd7..e64ae40 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 -# This file is Copyright (c) 2018-2019 Florent Kermarrec # This file is Copyright (c) 2018-2019 Rohit Singh +# This file is Copyright (c) 2019 Florent Kermarrec # License: BSD import sys @@ -28,8 +28,7 @@ from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litex_boards.platforms import nereid -# sdram module -# -------------------------------------------------------------------------------------------------- +# SDRAM Module ------------------------------------------------------------------------------------- class MT8KTF51264(SDRAMModule): memtype = "DDR3" @@ -65,7 +64,7 @@ class CRG(Module): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -# NereidSoC ------------------------------------------------------------------------------------------ +# NereidSoC ---------------------------------------------------------------------------------------- class NereidSoC(SoCSDRAM): SoCSDRAM.mem_map["csr"] = 0x00000000 @@ -73,9 +72,6 @@ class NereidSoC(SoCSDRAM): def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) - - # soc sdram - # ------------------------------------------------------------------------------------------ SoCSDRAM.__init__(self, platform, sys_clk_freq, csr_data_width=32, integrated_rom_size=0x10000, @@ -84,23 +80,19 @@ class NereidSoC(SoCSDRAM): ident="Nereid LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) - # crg - # ------------------------------------------------------------------------------------------ + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # dna - # ------------------------------------------------------------------------------------------ + # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") - # xadc - # ------------------------------------------------------------------------------------------ + # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") - # sdram - # ------------------------------------------------------------------------------------------ + # SDRAM ------------------------------------------------------------------------------------ if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), @@ -112,8 +104,7 @@ class NereidSoC(SoCSDRAM): sdram_module.timing_settings) self.add_csr("ddrphy") - # pcie - # ------------------------------------------------------------------------------------------ + # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") @@ -127,7 +118,8 @@ class NereidSoC(SoCSDRAM): self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge - self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base) + self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, + lambda a: 1, shadow_base=self.shadow_base) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma @@ -147,8 +139,7 @@ class NereidSoC(SoCSDRAM): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) - # pcie_uart - # ------------------------------------------------------------------------------------------ + # pcie uart if with_pcie_uart: class PCIeUART(Module, AutoCSR): def __init__(self, uart): @@ -189,8 +180,7 @@ class NereidSoC(SoCSDRAM): self.submodules.pcie_uart = PCIeUART(uart_interface) self.add_csr("pcie_uart") - # leds - # ------------------------------------------------------------------------------------------ + # Leds ------------------------------------------------------------------------------------- # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py index 0ed1ff4..763974a 100755 --- a/litex_boards/partner/targets/tagus.py +++ b/litex_boards/partner/targets/tagus.py @@ -1,7 +1,8 @@ #!/usr/bin/env python3 -# This file is Copyright (c) 2018-2019 Florent Kermarrec # This file is Copyright (c) 2018-2019 Rohit Singh +# This file is Copyright (c) 2019 Florent Kermarrec + # License: BSD import sys @@ -56,9 +57,6 @@ class TagusSoC(SoCSDRAM): def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) - - # soc sdram - # ------------------------------------------------------------------------------------------ SoCSDRAM.__init__(self, platform, sys_clk_freq, csr_data_width=32, integrated_rom_size=0x10000, @@ -67,23 +65,19 @@ class TagusSoC(SoCSDRAM): ident="Tagus LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) - # crg - # ------------------------------------------------------------------------------------------ + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # dna - # ------------------------------------------------------------------------------------------ + # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") - # xadc - # ------------------------------------------------------------------------------------------ + # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") - # sdram - # ------------------------------------------------------------------------------------------ + # SDRAM ------------------------------------------------------------------------------------ if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), @@ -95,8 +89,7 @@ class TagusSoC(SoCSDRAM): sdram_module.timing_settings) self.add_csr("ddrphy") - # pcie - # ------------------------------------------------------------------------------------------ + # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") @@ -110,7 +103,8 @@ class TagusSoC(SoCSDRAM): self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge - self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base) + self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, + lambda a: 1, shadow_base=self.shadow_base) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma @@ -131,7 +125,6 @@ class TagusSoC(SoCSDRAM): self.add_constant(k + "_INTERRUPT", i) # pcie_uart - # ------------------------------------------------------------------------------------------ if with_pcie_uart: class PCIeUART(Module, AutoCSR): def __init__(self, uart): @@ -172,8 +165,7 @@ class TagusSoC(SoCSDRAM): self.submodules.pcie_uart = PCIeUART(uart_interface) self.add_csr("pcie_uart") - # leds - # ------------------------------------------------------------------------------------------ + # Leds ------------------------------------------------------------------------------------- # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) From b4eefa6c33ca6a8047da7cafc777d4caa254a34e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 3 Sep 2019 15:23:40 +0200 Subject: [PATCH 6/8] import: allow importing directly from litex_boards.platforms or litex_boards.targets --- litex_boards/community/platforms/__init__.py | 6 ------ litex_boards/community/targets/__init__.py | 5 ----- litex_boards/official/platforms/__init__.py | 12 ------------ litex_boards/official/targets/__init__.py | 10 ---------- litex_boards/partner/platforms/__init__.py | 10 ---------- litex_boards/partner/targets/__init__.py | 6 ------ litex_boards/platforms.py | 18 +++++++++++++++--- litex_boards/targets.py | 18 +++++++++++++++--- 8 files changed, 30 insertions(+), 55 deletions(-) diff --git a/litex_boards/community/platforms/__init__.py b/litex_boards/community/platforms/__init__.py index dd11bf3..e69de29 100644 --- a/litex_boards/community/platforms/__init__.py +++ b/litex_boards/community/platforms/__init__.py @@ -1,6 +0,0 @@ -from litex_boards.community.platforms import ac701 -from litex_boards.community.platforms import de10lite -from litex_boards.community.platforms import de1soc -from litex_boards.community.platforms import de2_115 -from litex_boards.community.platforms import ecp5_evn -from litex_boards.community.platforms import sp605 diff --git a/litex_boards/community/targets/__init__.py b/litex_boards/community/targets/__init__.py index a1fcf29..e69de29 100644 --- a/litex_boards/community/targets/__init__.py +++ b/litex_boards/community/targets/__init__.py @@ -1,5 +0,0 @@ -#from litex_boards.community.targets import ac701 -#from litex_boards.community.targets import de10lite -#from litex_boards.community.targets import de1soc -#from litex_boards.community.targets import de2_115 -#from litex_boards.community.targets import ecp5_evn diff --git a/litex_boards/official/platforms/__init__.py b/litex_boards/official/platforms/__init__.py index 7661cf1..e69de29 100644 --- a/litex_boards/official/platforms/__init__.py +++ b/litex_boards/official/platforms/__init__.py @@ -1,12 +0,0 @@ -from litex_boards.official.platforms import arty -from litex_boards.official.platforms import avalanche -from litex_boards.official.platforms import de0nano -from litex_boards.official.platforms import genesys2 -from litex_boards.official.platforms import kc705 -from litex_boards.official.platforms import kcu105 -from litex_boards.official.platforms import machxo3 -from litex_boards.official.platforms import minispartan6 -from litex_boards.official.platforms import nexys4ddr -from litex_boards.official.platforms import nexys_video -from litex_boards.official.platforms import versa_ecp3 -from litex_boards.official.platforms import versa_ecp5 diff --git a/litex_boards/official/targets/__init__.py b/litex_boards/official/targets/__init__.py index 985dbcd..e69de29 100644 --- a/litex_boards/official/targets/__init__.py +++ b/litex_boards/official/targets/__init__.py @@ -1,10 +0,0 @@ -#from litex_boards.official.targets import arty -#from litex_boards.official.targets import de0nano -#from litex_boards.official.targets import genesys2 -#from litex_boards.official.targets import kc705 -#from litex_boards.official.targets import kcu105 -#from litex_boards.official.targets import minispartan6 -#from litex_boards.official.targets import nexys4ddr -#from litex_boards.official.targets import nexys_video -#from litex_boards.official.targets import simple -#from litex_boards.official.targets import versa_ecp5 diff --git a/litex_boards/partner/platforms/__init__.py b/litex_boards/partner/platforms/__init__.py index d5aef64..e69de29 100644 --- a/litex_boards/partner/platforms/__init__.py +++ b/litex_boards/partner/platforms/__init__.py @@ -1,10 +0,0 @@ -from litex_boards.partner.platforms import aller -from litex_boards.partner.platforms import fomu_evt -from litex_boards.partner.platforms import fomu_hacker -from litex_boards.partner.platforms import fomu_pvt -from litex_boards.partner.platforms import nereid -from litex_boards.partner.platforms import netv2 -from litex_boards.partner.platforms import tagus -from litex_boards.partner.platforms import tinyfpga_bx -from litex_boards.partner.platforms import trellisboard -from litex_boards.partner.platforms import ulx3s diff --git a/litex_boards/partner/targets/__init__.py b/litex_boards/partner/targets/__init__.py index e0b9ba5..e69de29 100644 --- a/litex_boards/partner/targets/__init__.py +++ b/litex_boards/partner/targets/__init__.py @@ -1,6 +0,0 @@ -#from litex_boards.partner.targets import aller -#from litex_boards.partner.targets import nereid -#from litex_boards.partner.targets import netv2 -#from litex_boards.partner.targets import tagus -#from litex_boards.partner.targets import trellisboard -#from litex_boards.partner.targets import ulx3s diff --git a/litex_boards/platforms.py b/litex_boards/platforms.py index 363554b..ffa4b03 100644 --- a/litex_boards/platforms.py +++ b/litex_boards/platforms.py @@ -1,3 +1,15 @@ -from litex_boards.official.platforms import * -from litex_boards.partner.platforms import * -from litex_boards.community.platforms import * +import sys +import importlib + +class Platforms: + def __getattr__(self, name): + if name == "__path__": + return [] + for support in ["official", "partner", "community"]: + try: + return importlib.import_module("litex_boards." + support + ".platforms." + name) + except: + pass + raise ModuleNotFoundError + +sys.modules[__name__] = Platforms() diff --git a/litex_boards/targets.py b/litex_boards/targets.py index 9f35cde..8ae7041 100644 --- a/litex_boards/targets.py +++ b/litex_boards/targets.py @@ -1,3 +1,15 @@ -from litex_boards.official.targets import * -from litex_boards.partner.targets import * -from litex_boards.community.targets import * +import sys +import importlib + +class Targets: + def __getattr__(self, name): + if name == "__path__": + return [] + for support in ["official", "partner", "community"]: + try: + return importlib.import_module("litex_boards." + support + ".targets." + name) + except: + pass + raise ModuleNotFoundError + +sys.modules[__name__] = Targets() From c6bb34d78a9106eafa0b3c0935ec9c30557574ee Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Sep 2019 08:50:06 +0200 Subject: [PATCH 7/8] partner/targets/nereid: MT8KTF51264 now in LiteDRAM --- litex_boards/partner/targets/nereid.py | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index e64ae40..f700e24 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -17,7 +17,7 @@ from litex.soc.cores import dna, xadc from litex.soc.cores.uart import * from litex.soc.integration.cpu_interface import get_csr_header -from litedram.modules import SDRAMModule +from litedram.modules import MT8KTF51264 from litedram.modules import _TechnologyTimings, _SpeedgradeTimings from litedram.phy import s7ddrphy @@ -28,23 +28,6 @@ from litepcie.frontend.wishbone import LitePCIeWishboneBridge from litex_boards.platforms import nereid -# SDRAM Module ------------------------------------------------------------------------------------- - -class MT8KTF51264(SDRAMModule): - memtype = "DDR3" - # geometry - nbanks = 8 - nrows = 16384 - ncols = 1024 - # timings - technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10)) - speedgrade_timings = { - "800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=260, tFAW=(None, 50), tRAS=None), - "1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRAS=None), - "1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRAS=None), - } - speedgrade_timings["default"] = speedgrade_timings["1333"] - # CRG ---------------------------------------------------------------------------------------------- class CRG(Module): From 91a1520655405f821c7b3552d5d98da008747b3c Mon Sep 17 00:00:00 2001 From: Antti Lukats Date: Tue, 10 Sep 2019 11:25:57 +0200 Subject: [PATCH 8/8] add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet --- litex_boards/partner/platforms/c10lprefkit.py | 125 ++++++++++++++ litex_boards/partner/targets/c10lprefkit.py | 155 ++++++++++++++++++ 2 files changed, 280 insertions(+) create mode 100644 litex_boards/partner/platforms/c10lprefkit.py create mode 100755 litex_boards/partner/targets/c10lprefkit.py diff --git a/litex_boards/partner/platforms/c10lprefkit.py b/litex_boards/partner/platforms/c10lprefkit.py new file mode 100644 index 0000000..20c8102 --- /dev/null +++ b/litex_boards/partner/platforms/c10lprefkit.py @@ -0,0 +1,125 @@ +# This file is Copyright (c) 2019 Antti Lukats +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + ("clk12", 0, Pins("G21"), IOStandard("3.3-V LVTTL")), + ("clk25", 0, Pins("AA12"), IOStandard("3.3-V LVTTL")), + + ("user_led", 0, Pins("C18"), IOStandard("3.3-V LVTTL")), + ("user_led", 1, Pins("D19"), IOStandard("3.3-V LVTTL")), + ("user_led", 2, Pins("C19"), IOStandard("3.3-V LVTTL")), + ("user_led", 3, Pins("C17"), IOStandard("3.3-V LVTTL")), + ("user_led", 4, Pins("D18"), IOStandard("3.3-V LVTTL")), + + + ("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")), + + ("sw", 0, Pins("U10"), IOStandard("3.3-V LVTTL")), + ("sw", 1, Pins("U11"), IOStandard("3.3-V LVTTL")), + ("sw", 2, Pins("V11"), IOStandard("3.3-V LVTTL")), + ("sw", 3, Pins("T10"), IOStandard("3.3-V LVTTL")), + ("sw", 4, Pins("T11"), IOStandard("3.3-V LVTTL")), + + ("serial", 0, + Subsignal("tx", Pins("B21"), IOStandard("3.3-V LVTTL")), + Subsignal("rx", Pins("C20"), IOStandard("3.3-V LVTTL")), + ), + + ("sdram_clock", 0, Pins("AA3"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins( + "V5 Y3 W6 Y4 AB5 AB6 AA6 AA7", + "AB7 AA5 V6 AA8 AB8")), + Subsignal("ba", Pins("Y6 V7")), + Subsignal("cs_n", Pins("W7")), + Subsignal("cke", Pins("AA4")), + Subsignal("ras_n", Pins("V8")), + Subsignal("cas_n", Pins("Y7")), + Subsignal("we_n", Pins("W8")), + Subsignal("dq", Pins( + "AB16 Y17 AA16 AA19 AB18 AA20 AB19 AB20", + "Y13 Y15 AA13 AB15 AB13 AA15 AA14 AB14")), + Subsignal("dm", Pins("Y14 W13")), + IOStandard("3.3-V LVTTL") + ), + + ("epcs", 0, + Subsignal("data0", Pins("K1")), + Subsignal("dclk", Pins("K2")), + Subsignal("ncs0", Pins("E2")), + Subsignal("asd0", Pins("D1")), + IOStandard("3.3-V LVTTL") + ), + + ("hyperram", 0, + Subsignal("clk", Pins("T16")), + Subsignal("rst_n", Pins("U12")), + Subsignal("dq", Pins("T15 W17 U14 R15 R14 V16 U16 U17")), + Subsignal("cs_n", Pins("V13")), + Subsignal("rwds", Pins("U13")), + IOStandard("3.3-V LVTTL") + ), + + ("gpio_leds", 0, + Pins("AB10 AA10 AA9 Y10 W10 U9 U8 U7"), + IOStandard("3.3-V LVTTL") + ), + + ("eth_clocks", 0, + Subsignal("tx", Pins("U21")), + Subsignal("rx", Pins("V22")), + IOStandard("3.3-V LVTTL"), + ), + ("eth", 0, + Subsignal("rst_n", Pins("R19")), + Subsignal("mdio", Pins("AA21")), + Subsignal("mdc", Pins("AA22")), + Subsignal("rx_dv", Pins("W21")), + Subsignal("rx_er", Pins("V21")), + Subsignal("rx_data", Pins("W22 W20 Y21 Y22")), + Subsignal("tx_en", Pins("T18")), + Subsignal("tx_data", Pins("T17 U20 U19 T20")), + Subsignal("col", Pins("T19")), + Subsignal("crs", Pins("R20")), + IOStandard("3.3-V LVTTL"), + ), + + ("eth_clocks", 1, + Subsignal("tx", Pins("N16")), + Subsignal("rx", Pins("V22")), + IOStandard("3.3-V LVTTL"), + ), + ("eth", 1, + Subsignal("rst_n", Pins("M21")), + Subsignal("mdio", Pins("N20")), + Subsignal("mdc", Pins("N18")), + Subsignal("rx_dv", Pins("R18")), + Subsignal("rx_er", Pins("P17")), + Subsignal("rx_data", Pins("M20 M19 M16 N19")), + Subsignal("tx_en", Pins("R22")), + Subsignal("tx_data", Pins("R21 N21 M22 N22")), + Subsignal("col", Pins("P21")), + Subsignal("crs", Pins("P22")), + IOStandard("3.3-V LVTTL"), + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk12" + default_clk_period = 1e9/12e6 + + def __init__(self): + AlteraPlatform.__init__(self, "10CL055YU484A7G", _io) + self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone 10 LP\"") + + def create_programmer(self): + return USBBlaster() diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py new file mode 100755 index 0000000..3b95fa8 --- /dev/null +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -0,0 +1,155 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2019 Antti Lukats +# This file is Copyright (c) 2019 msloniewski +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD + +import argparse + +from migen import * + +from litex_boards.platforms import c10lprefkit + +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * + +from litedram.modules import MT48LC16M16 +from litedram.phy import GENSDRPHY + +from liteeth.phy.mii import LiteEthPHYMII +from liteeth.mac import LiteEthMAC + +from litex.soc.cores.hyperbus import HyperRAM + +# CRG ---------------------------------------------------------------------------------------------- +class _CRG(Module): + def __init__(self, platform): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys_ps.clk.attr.add("keep") + self.cd_por.clk.attr.add("keep") + + clk12 = platform.request("clk12") + + # power on rst + rst_n = Signal() + self.sync.por += rst_n.eq(platform.request("cpu_reset")) + self.comb += [ + self.cd_por.clk.eq(clk12), + self.cd_sys.rst.eq(~rst_n), + self.cd_sys_ps.rst.eq(~rst_n) + ] + + # sys clk / sdram clk + clk_outs = Signal(5) + self.specials += \ + Instance("ALTPLL", + p_BANDWIDTH_TYPE="AUTO", + p_CLK0_DIVIDE_BY=6, + p_CLK0_DUTY_CYCLE=50, + p_CLK0_MULTIPLY_BY=25, + p_CLK0_PHASE_SHIFT="0", + p_CLK1_DIVIDE_BY=6, + p_CLK1_DUTY_CYCLE=50, + p_CLK1_MULTIPLY_BY=25, + p_CLK1_PHASE_SHIFT="-10000", + p_COMPENSATE_CLOCK="CLK0", + p_INCLK0_INPUT_FREQUENCY=83000, + p_INTENDED_DEVICE_FAMILY="MAX 10", + p_LPM_TYPE="altpll", + p_OPERATION_MODE="NORMAL", + i_INCLK=clk12, + o_CLK=clk_outs, + i_ARESET=0, + i_CLKENA=0x3f, + i_EXTCLKENA=0xf, + i_FBIN=1, + i_PFDENA=1, + i_PLLENA=1, + ) + self.comb += self.cd_sys.clk.eq(clk_outs[0]) + self.comb += self.cd_sys_ps.clk.eq(clk_outs[1]) + self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCSDRAM): + mem_map = { + "hyperram": 0x20000000, + } + mem_map.update(SoCCore.mem_map) + + + def __init__(self, sys_clk_freq=int(50e6), **kwargs): + assert sys_clk_freq == int(50e6) + platform = c10lprefkit.Platform() + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + **kwargs) + + self.submodules.crg = _CRG(platform) + + self.submodules.hyperram = HyperRAM(platform.request("hyperram")) + self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus) + self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024) + + if not self.integrated_main_ram_size: + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdram_module = MT48LC16M16(self.clk_freq, "1:1") + self.register_sdram(self.sdrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + + +class EthernetSoC(BaseSoC): + mem_map = { + "ethmac": 0x30000000, # (shadow @0xb0000000) + } + mem_map.update(BaseSoC.mem_map) + + def __init__(self, eth_port=0, **kwargs): + BaseSoC.__init__(self, **kwargs) + + self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks", eth_port), + self.platform.request("eth", eth_port)) + self.add_csr("ethphy") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, + interface="wishbone", endianness=self.cpu.endianness) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") + self.add_interrupt("ethmac") + + self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").tx, 1e9/12.5e6) + self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").rx, 1e9/12.5e6) + self.platform.add_false_path_constraints( + self.platform.lookup_request("clk12"), + self.platform.lookup_request("eth_clocks").tx, + self.platform.lookup_request("eth_clocks").rx + ) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") + builder_args(parser) + soc_sdram_args(parser) + parser.add_argument("--with-ethernet", action="store_true", + help="enable Ethernet support") + args = parser.parse_args() + + cls = EthernetSoC if args.with_ethernet else BaseSoC + soc = cls(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main()