Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

qmtech_wukong: Minor cleanups.

This commit is contained in:
Florent Kermarrec 2024-03-28 14:50:03 +01:00
parent 57a9970257
commit 9235468ce1
2 changed files with 59 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
litex_boards/platforms/qmtech_wukong.py
View File

@ -10,32 +10,32 @@ from litex.build.openocd import OpenOCD
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
# IOs specific to V1 of the board # IOs specific to V1 of the board.
_io_v1 = [ _io_v1 = [
# Reset (Key1 button) # Reset (Key1 button).
("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")), # key1 ("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")),
#Clock # Clock.
("clk50" , 0, Pins("M22"), IOStandard("LVCMOS33")), ("clk50" , 0, Pins("M22"), IOStandard("LVCMOS33")),
# Leds # Leds.
("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")),
] ]
# IOs specific to V2 of the board # IOs specific to V2 of the board.
_io_v2 = [ _io_v2 = [
# Reset (Key1 button) # Reset (Key1 button).
("cpu_reset", 0, Pins("M6"), IOStandard("LVCMOS33")), ("cpu_reset", 0, Pins("M6"), IOStandard("LVCMOS33")),
# Clock # Clock.
("clk50" , 0, Pins("M21"), IOStandard("LVCMOS33")), ("clk50" , 0, Pins("M21"), IOStandard("LVCMOS33")),
# Leds # Leds.
("user_led", 0, Pins("V16"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("V16"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("V17"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("V17"), IOStandard("LVCMOS33")),
# SD-Card # SD-Card.
("sdcard", 0, ("sdcard", 0,
Subsignal("data", Pins("M5 M7 H6 J6")), Subsignal("data", Pins("M5 M7 H6 J6")),
Subsignal("cmd", Pins("J8")), Subsignal("cmd", Pins("J8")),
@ -46,19 +46,19 @@ _io_v2 = [
), ),
] ]
# IO commons to both versions of the board # IO commons to both versions of the board.
_io_common = [ _io_common = [
# Key0 button (Key1 is used as cpu reset and is version specific) # Key0 button (Key1 is used as cpu reset and is version specific).
("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")), ("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")),
# Serial # Serial.
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("E3")), Subsignal("tx", Pins("E3")),
Subsignal("rx", Pins("F3")), Subsignal("rx", Pins("F3")),
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
), ),
# SPIFlash # SPIFlash.
("spiflash", 0, ("spiflash", 0,
Subsignal("cs_n", Pins("P18")), Subsignal("cs_n", Pins("P18")),
Subsignal("clk", Pins("H13")), Subsignal("clk", Pins("H13")),
@ -75,7 +75,7 @@ _io_common = [
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
# DDR3 SDRAM # DDR3 SDRAM.
("ddram", 0, ("ddram", 0,
Subsignal("a", Pins( Subsignal("a", Pins(
"E17 G17 F17 C17 G16 D16 H16 E16", "E17 G17 F17 C17 G16 D16 H16 E16",
@ -108,7 +108,7 @@ _io_common = [
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
), ),
# GMII Ethernet # GMII Ethernet.
("eth_clocks", 0, ("eth_clocks", 0,
Subsignal("tx", Pins("M2")), Subsignal("tx", Pins("M2")),
Subsignal("gtx", Pins("U1")), Subsignal("gtx", Pins("U1")),
@ -130,7 +130,7 @@ _io_common = [
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
# HDMI out # HDMI out.
("hdmi_out", 0, ("hdmi_out", 0,
Subsignal("clk_p", Pins("D4"), IOStandard("TMDS_33")), Subsignal("clk_p", Pins("D4"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("C4"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("C4"), IOStandard("TMDS_33")),
@ -157,7 +157,7 @@ _connectors = [
" V26 W26 U25 U26 V24 W24 V23 W23", " V26 W26 U25 U26 V24 W24 V23 W23",
" V18 W18 U22 V22 U21 V21 T20 U20", " V18 W18 U22 V22 U21 V21 T20 U20",
" T19 U19"), " T19 U19"),
("jp2", "H21 H22 K21 J21 H26 G26 G25 F25", ("jp2", " H21 H22 K21 J21 H26 G26 G25 F25",
"G20 G21 F23 E23 E26 D26 E25 D25"), "G20 G21 F23 E23 E26 D26 E25 D25"),
("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD10 AC10", ("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD10 AC10",
"AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13", "AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13",
@ -200,13 +200,15 @@ class Platform(Xilinx7SeriesPlatform):
default_clk_name = "clk50" default_clk_name = "clk50"
default_clk_period = 1e9/50e6 default_clk_period = 1e9/50e6
def __init__(self, board_version=1, speed_grade=-2, toolchain="vivado"): def __init__(self, board_version=1, speedgrade=-2, toolchain="vivado"):
io = _io_common io = _io_common
if speedgrade not in [-1,-2]:
raise ValueError(f"Speedgrade {speedgrade} unsupported.")
if board_version < 2: if board_version < 2:
io.extend(_io_v1) io.extend(_io_v1)
else: else:
io.extend(_io_v2) io.extend(_io_v2)
Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain=toolchain) Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speedgrade), io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \ self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]

69
litex_boards/targets/qmtech_wukong.py
View File

@ -41,38 +41,40 @@ class _CRG(LiteXModule):
# # # # # #
plls_reset = platform.request("cpu_reset") # Clk/Rst.
plls_clk50 = platform.request("clk50") clk50 = platform.request("clk50")
rst = platform.request("cpu_reset")
# Main PLL.
self.pll = pll = S7MMCM(speedgrade=speed_grade) self.pll = pll = S7MMCM(speedgrade=speed_grade)
self.comb += pll.reset.eq(~plls_reset | self.rst) self.comb += pll.reset.eq(~rst | self.rst)
pll.register_clkin(plls_clk50, 50e6) pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
#pll.create_clkout(self.cd_idelay, 200e6)
# idelay PLL # IDelay PLL.
self.pll_idelay = pll_idelay = S7PLL(speedgrade=speed_grade) self.pll_idelay = pll_idelay = S7PLL(speedgrade=speed_grade)
self.comb += pll_idelay.reset.eq(~plls_reset | self.rst) self.comb += pll_idelay.reset.eq(~rst | self.rst)
pll_idelay.register_clkin(plls_clk50, 50e6) pll_idelay.register_clkin(clk50, 50e6)
pll_idelay.create_clkout(self.cd_idelay, 200e6) pll_idelay.create_clkout(self.cd_idelay, 200e6)
pll_idelay.create_clkout(self.cd_clk100, 100e6) pll_idelay.create_clkout(self.cd_clk100, 100e6)
# IDelayCtrl.
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# Video PLL. # Video PLL.
if with_video_pll: if with_video_pll:
self.video_pll = video_pll = S7MMCM(speedgrade=speed_grade) self.video_pll = video_pll = S7MMCM(speedgrade=speed_grade)
self.comb += video_pll.reset.eq(~plls_reset | self.rst) self.comb += video_pll.reset.eq(~rst | self.rst)
video_pll.register_clkin(plls_clk50, 50e6) video_pll.register_clkin(clk50, 50e6)
video_pll.create_clkout(self.cd_hdmi, pix_clk) video_pll.create_clkout(self.cd_hdmi, pix_clk)
video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk) video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6, board_version=1, speed_grade=-2, def __init__(self, sys_clk_freq=100e6, board_version=1, speedgrade=-2,
with_ethernet = False, with_ethernet = False,
with_etherbone = False, with_etherbone = False,
eth_ip = "192.168.1.50", eth_ip = "192.168.1.50",
@ -81,17 +83,17 @@ class BaseSoC(SoCCore):
with_video_framebuffer = False, with_video_framebuffer = False,
video_timing = "640x480@60Hz", video_timing = "640x480@60Hz",
**kwargs): **kwargs):
platform = qmtech_wukong.Platform(board_version=board_version,speed_grade=speed_grade) platform = qmtech_wukong.Platform(board_version=board_version,speedgrade=speedgrade)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
with_video_pll = (with_video_terminal or with_video_framebuffer) with_video_pll = (with_video_terminal or with_video_framebuffer)
self.crg = _CRG(platform, speed_grade, sys_clk_freq, self.crg = _CRG(platform, speedgrade, sys_clk_freq,
with_video_pll = with_video_pll, with_video_pll = with_video_pll,
pix_clk = video_timings[video_timing]["pix_clk"] pix_clk = video_timings[video_timing]["pix_clk"]
) )
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QMTECH Wukong Board", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident=f"LiteX SoC on QMTECH Wukong Board V{board_version}", **kwargs)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
@ -122,44 +124,41 @@ class BaseSoC(SoCCore):
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
# Video ----------------------------------- ------------------------------------------------- # Video ----------------------------------- -------------------------------------------------
if with_video_terminal or with_video_framebuffer: if with_video_terminal or with_video_framebuffer:
self.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi") self.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
if with_video_terminal: if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings=video_timing, clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings=video_timing, clock_domain="hdmi")
if with_video_framebuffer: if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings=video_timing, clock_domain="hdmi") self.add_video_framebuffer(phy=self.videophy, timings=video_timing, clock_domain="hdmi")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board.") parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--board-version", default=1, help="Board version (1 or 2).") parser.add_target_argument("--board-version", default=1, help="Board version (1 or 2).")
parser.add_target_argument("--speed-grade", default=-1, help="FPGA speed grade (-1 or -2).") parser.add_target_argument("--speedgrade", default=-1, help="FPGA speedgrade (-1 or -2).")
ethopts = parser.target_group.add_mutually_exclusive_group() ethopts = parser.target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.") parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
sdopts = parser.target_group.add_mutually_exclusive_group() sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = parser.target_group.add_mutually_exclusive_group() viopts = parser.target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
args = parser.parse_args() args = parser.parse_args()
speed_grade = int(args.speed_grade)
if speed_grade not in [-1,-2]:
raise ValueError("Speed grade {} unsupported".format(speed_grade))
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq, sys_clk_freq = args.sys_clk_freq,
board_version = int(args.board_version), board_version = int(args.board_version),
speed_grade = speed_grade, speedgrade = args.speedgrade,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip, eth_ip = args.eth_ip,
with_video_terminal = args.with_video_terminal, with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer, with_video_framebuffer = args.with_video_framebuffer,
**parser.soc_argdict **parser.soc_argdict