qmtech_wukong: Minor cleanups.
This commit is contained in:
Florent Kermarrec
parent
57a9970257
commit
9235468ce1
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@ -10,32 +10,32 @@ from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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# IOs specific to V1 of the board
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# IOs specific to V1 of the board.
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_io_v1 = [
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# Reset (Key1 button)
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("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")), # key1
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# Reset (Key1 button).
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("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")),
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#Clock
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("clk50" , 0, Pins("M22"), IOStandard("LVCMOS33")),
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# Clock.
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("clk50" , 0, Pins("M22"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")),
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# Leds.
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("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")),
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]
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# IOs specific to V2 of the board
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# IOs specific to V2 of the board.
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_io_v2 = [
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# Reset (Key1 button)
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# Reset (Key1 button).
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("cpu_reset", 0, Pins("M6"), IOStandard("LVCMOS33")),
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# Clock
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# Clock.
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("clk50" , 0, Pins("M21"), IOStandard("LVCMOS33")),
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# Leds
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# Leds.
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("user_led", 0, Pins("V16"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("V17"), IOStandard("LVCMOS33")),
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# SD-Card
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# SD-Card.
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("sdcard", 0,
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Subsignal("data", Pins("M5 M7 H6 J6")),
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Subsignal("cmd", Pins("J8")),
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@ -46,19 +46,19 @@ _io_v2 = [
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),
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]
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# IO commons to both versions of the board
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# IO commons to both versions of the board.
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_io_common = [
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# Key0 button (Key1 is used as cpu reset and is version specific)
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# Key0 button (Key1 is used as cpu reset and is version specific).
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("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")),
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# Serial
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("E3")),
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Subsignal("rx", Pins("F3")),
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IOStandard("LVCMOS33"),
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),
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# SPIFlash
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# SPIFlash.
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("spiflash", 0,
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Subsignal("cs_n", Pins("P18")),
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Subsignal("clk", Pins("H13")),
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@ -75,7 +75,7 @@ _io_common = [
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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"E17 G17 F17 C17 G16 D16 H16 E16",
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@ -108,7 +108,7 @@ _io_common = [
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Misc("SLEW=FAST"),
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),
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# GMII Ethernet
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# GMII Ethernet.
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("eth_clocks", 0,
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Subsignal("tx", Pins("M2")),
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Subsignal("gtx", Pins("U1")),
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@ -130,7 +130,7 @@ _io_common = [
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IOStandard("LVCMOS33")
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),
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# HDMI out
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# HDMI out.
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("D4"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("C4"), IOStandard("TMDS_33")),
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@ -157,7 +157,7 @@ _connectors = [
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" V26 W26 U25 U26 V24 W24 V23 W23",
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" V18 W18 U22 V22 U21 V21 T20 U20",
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" T19 U19"),
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("jp2", "H21 H22 K21 J21 H26 G26 G25 F25",
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("jp2", " H21 H22 K21 J21 H26 G26 G25 F25",
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"G20 G21 F23 E23 E26 D26 E25 D25"),
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("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD10 AC10",
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"AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13",
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@ -200,13 +200,15 @@ class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, board_version=1, speed_grade=-2, toolchain="vivado"):
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def __init__(self, board_version=1, speedgrade=-2, toolchain="vivado"):
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io = _io_common
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if speedgrade not in [-1,-2]:
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raise ValueError(f"Speedgrade {speedgrade} unsupported.")
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if board_version < 2:
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io.extend(_io_v1)
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else:
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io.extend(_io_v2)
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Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain=toolchain)
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Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speedgrade), io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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@ -41,38 +41,40 @@ class _CRG(LiteXModule):
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# # #
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plls_reset = platform.request("cpu_reset")
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plls_clk50 = platform.request("clk50")
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# Clk/Rst.
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clk50 = platform.request("clk50")
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rst = platform.request("cpu_reset")
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# Main PLL.
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self.pll = pll = S7MMCM(speedgrade=speed_grade)
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self.comb += pll.reset.eq(~plls_reset | self.rst)
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pll.register_clkin(plls_clk50, 50e6)
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self.comb += pll.reset.eq(~rst | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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#pll.create_clkout(self.cd_idelay, 200e6)
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# idelay PLL
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# IDelay PLL.
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self.pll_idelay = pll_idelay = S7PLL(speedgrade=speed_grade)
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self.comb += pll_idelay.reset.eq(~plls_reset | self.rst)
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pll_idelay.register_clkin(plls_clk50, 50e6)
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self.comb += pll_idelay.reset.eq(~rst | self.rst)
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pll_idelay.register_clkin(clk50, 50e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6)
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pll_idelay.create_clkout(self.cd_clk100, 100e6)
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# IDelayCtrl.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# Video PLL.
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if with_video_pll:
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self.video_pll = video_pll = S7MMCM(speedgrade=speed_grade)
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self.comb += video_pll.reset.eq(~plls_reset | self.rst)
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video_pll.register_clkin(plls_clk50, 50e6)
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self.comb += video_pll.reset.eq(~rst | self.rst)
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video_pll.register_clkin(clk50, 50e6)
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video_pll.create_clkout(self.cd_hdmi, pix_clk)
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video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, board_version=1, speed_grade=-2,
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def __init__(self, sys_clk_freq=100e6, board_version=1, speedgrade=-2,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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@ -81,17 +83,17 @@ class BaseSoC(SoCCore):
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with_video_framebuffer = False,
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video_timing = "640x480@60Hz",
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**kwargs):
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platform = qmtech_wukong.Platform(board_version=board_version,speed_grade=speed_grade)
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platform = qmtech_wukong.Platform(board_version=board_version,speedgrade=speedgrade)
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# CRG --------------------------------------------------------------------------------------
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with_video_pll = (with_video_terminal or with_video_framebuffer)
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self.crg = _CRG(platform, speed_grade, sys_clk_freq,
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self.crg = _CRG(platform, speedgrade, sys_clk_freq,
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with_video_pll = with_video_pll,
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pix_clk = video_timings[video_timing]["pix_clk"]
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)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QMTECH Wukong Board", **kwargs)
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SoCCore.__init__(self, platform, sys_clk_freq, ident=f"LiteX SoC on QMTECH Wukong Board V{board_version}", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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@ -122,44 +124,41 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Video ----------------------------------- -------------------------------------------------
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# Video ----------------------------------- -------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings=video_timing, clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings=video_timing, clock_domain="hdmi")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--board-version", default=1, help="Board version (1 or 2).")
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parser.add_target_argument("--speed-grade", default=-1, help="FPGA speed grade (-1 or -2).")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--board-version", default=1, help="Board version (1 or 2).")
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parser.add_target_argument("--speedgrade", default=-1, help="FPGA speedgrade (-1 or -2).")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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args = parser.parse_args()
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speed_grade = int(args.speed_grade)
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if speed_grade not in [-1,-2]:
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raise ValueError("Speed grade {} unsupported".format(speed_grade))
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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board_version = int(args.board_version),
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speed_grade = speed_grade,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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sys_clk_freq = args.sys_clk_freq,
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board_version = int(args.board_version),
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speedgrade = args.speedgrade,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**parser.soc_argdict
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