From 1ab46562bd8fc1689f0119836878935f30d5286a Mon Sep 17 00:00:00 2001 From: Skip Hansen Date: Mon, 25 May 2020 10:11:03 -0700 Subject: [PATCH 1/2] Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200) --- litex_boards/platforms/pano_logic_g2.py | 3 +++ litex_boards/targets/pano_logic_g2.py | 6 ++++++ 2 files changed, 9 insertions(+) mode change 100644 => 100755 litex_boards/platforms/pano_logic_g2.py diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py old mode 100644 new mode 100755 index 3f83ce1..1462537 --- a/litex_boards/platforms/pano_logic_g2.py +++ b/litex_boards/platforms/pano_logic_g2.py @@ -97,6 +97,9 @@ _io = [ Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")), Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), ), + # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active) + ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")), + ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index 6c179b1..44f4a5b 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -46,6 +46,12 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq) self.add_csr("leds") + # Take Ethernet Phy out of reset for SYSCLK of 125 Mhz + gmii_rst_n = platform.request("gmii_rst_n") + self.comb += [ + gmii_rst_n.eq(1) + ] + # Build -------------------------------------------------------------------------------------------- def main(): From 0648c041589cb1c8452932483138996c0ec6a714 Mon Sep 17 00:00:00 2001 From: Skip Hansen Date: Mon, 25 May 2020 14:48:24 -0700 Subject: [PATCH 2/2] Updated comment, added link to clocking documentation. --- litex_boards/platforms/pano_logic_g2.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py index 1462537..76260bc 100755 --- a/litex_boards/platforms/pano_logic_g2.py +++ b/litex_boards/platforms/pano_logic_g2.py @@ -98,6 +98,7 @@ _io = [ Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), ), # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active) + # See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")), ]