From 936ba5b279f83cf3aab1336ff560c592fdd215d4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 23 Jun 2020 11:55:50 +0200
Subject: [PATCH] platforms/genesys2: add openocd specific configuration
 (channel 1 used for JTAG).

---
 litex_boards/platforms/genesys2.py     |  2 +-
 litex_boards/prog/openocd_genesys2.cfg | 14 ++++++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 litex_boards/prog/openocd_genesys2.cfg

diff --git a/litex_boards/platforms/genesys2.py b/litex_boards/platforms/genesys2.py
index 0dc8a5e..f81b132 100644
--- a/litex_boards/platforms/genesys2.py
+++ b/litex_boards/platforms/genesys2.py
@@ -134,7 +134,7 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
+        return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex_boards/prog/openocd_genesys2.cfg b/litex_boards/prog/openocd_genesys2.cfg
new file mode 100644
index 0000000..c7e09f1
--- /dev/null
+++ b/litex_boards/prog/openocd_genesys2.cfg
@@ -0,0 +1,14 @@
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_channel 1
+ftdi_layout_init 0x00e8 0x60eb
+reset_config none
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+adapter_khz 25000
+
+proc fpga_program {} {
+    global _CHIPNAME
+    xc7_program $_CHIPNAME.tap
+}