From 938bf8b3a63b54e25436182bbd45aab53d783c62 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 22 Jul 2024 15:18:27 +0200 Subject: [PATCH] targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR --- litex_boards/targets/lattice_certuspro_nx_evn.py | 2 +- litex_boards/targets/lattice_certuspro_nx_vvml.py | 2 +- litex_boards/targets/lattice_crosslink_nx_evn.py | 2 +- litex_boards/targets/lattice_crosslink_nx_vip.py | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/lattice_certuspro_nx_evn.py b/litex_boards/targets/lattice_certuspro_nx_evn.py index 9aa9438..465e850 100755 --- a/litex_boards/targets/lattice_certuspro_nx_evn.py +++ b/litex_boards/targets/lattice_certuspro_nx_evn.py @@ -39,7 +39,7 @@ class _CRG(LiteXModule): self.rst_n = platform.request("user_btn", 0) # Clocking - self.hf_clk = NXOSCA() + self.hf_clk = NXOSCA(platform) hf_clk_freq = 25e6 self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq) diff --git a/litex_boards/targets/lattice_certuspro_nx_vvml.py b/litex_boards/targets/lattice_certuspro_nx_vvml.py index 39a5ef3..d0e4b7c 100755 --- a/litex_boards/targets/lattice_certuspro_nx_vvml.py +++ b/litex_boards/targets/lattice_certuspro_nx_vvml.py @@ -39,7 +39,7 @@ class _CRG(LiteXModule): self.rst_n = platform.request("gsrn") # Built in OSC - self.hf_clk = NXOSCA() + self.hf_clk = NXOSCA(platform) hf_clk_freq = 25e6 self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq) diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index b6b6a0e..9ffcf6c 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -34,7 +34,7 @@ class _CRG(LiteXModule): self.cd_sys = ClockDomain() # Built in OSC - self.hf_clk = NXOSCA() + self.hf_clk = NXOSCA(platform) hf_clk_freq = 25e6 self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq) diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index 827a1e9..325bf1e 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -38,7 +38,7 @@ class _CRG(LiteXModule): # TODO: replace with PLL # Clocking - self.sys_clk = sys_osc = NXOSCA() + self.sys_clk = sys_osc = NXOSCA(platform) sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq) platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq) rst_n = platform.request("gsrn")