From 94861bbb9af6a3d0c59beb3fa6c9c0967532f6e2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Jun 2020 19:29:58 +0200 Subject: [PATCH] targets/orangecrab: uncomment MT41K512M16. --- litex_boards/targets/orangecrab.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 98cf0a1..a024d3d 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -18,7 +18,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16 +from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16 from litedram.phy import ECP5DDRPHY # _CRG --------------------------------------------------------------------------------------------- @@ -85,7 +85,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, revision = "0.2", device = "25F", sdram_device = "MT41K64M16", + def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16", sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) @@ -102,10 +102,10 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: available_sdram_modules = { - 'MT41K64M16': MT41K64M16, - 'MT41K128M16': MT41K128M16, - 'MT41K256M16': MT41K256M16, -# 'MT41K512M16': MT41K512M16 + "MT41K64M16": MT41K64M16, + "MT41K128M16": MT41K128M16, + "MT41K256M16": MT41K256M16, + "MT41K512M16": MT41K512M16 } sdram_module = available_sdram_modules.get(sdram_device)