diff --git a/litex_boards/platforms/kcu105.py b/litex_boards/platforms/kcu105.py
index 820293b..da916f3 100644
--- a/litex_boards/platforms/kcu105.py
+++ b/litex_boards/platforms/kcu105.py
@@ -498,6 +498,6 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 44]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 45]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 46]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
diff --git a/litex_boards/platforms/vcu118.py b/litex_boards/platforms/vcu118.py
index 4d1ab5a..19ed618 100644
--- a/litex_boards/platforms/vcu118.py
+++ b/litex_boards/platforms/vcu118.py
@@ -182,10 +182,10 @@ class Platform(XilinxPlatform):
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         # DDR4 memory channel C1 Internal Vref
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 71]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 72]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 73]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 73]")
         # DDR4 memory channel C2 Internal Vref
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 40]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 41]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 42]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]")
diff --git a/litex_boards/platforms/zcu104.py b/litex_boards/platforms/zcu104.py
index 1bf64c9..59c643f 100644
--- a/litex_boards/platforms/zcu104.py
+++ b/litex_boards/platforms/zcu104.py
@@ -142,5 +142,5 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 65]")
-        self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 66]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")