From 96175a9986432c1bddb3f0c265e9584a987673de Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 7 Jun 2023 15:00:49 +0200 Subject: [PATCH] sitlinv_stlv7325_v2: Add default value to vccio. --- litex_boards/platforms/sitlinv_stlv7325_v2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/sitlinv_stlv7325_v2.py b/litex_boards/platforms/sitlinv_stlv7325_v2.py index e0552a3..912a4fe 100644 --- a/litex_boards/platforms/sitlinv_stlv7325_v2.py +++ b/litex_boards/platforms/sitlinv_stlv7325_v2.py @@ -486,7 +486,7 @@ class Platform(Xilinx7SeriesPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self, vccio): + def __init__(self, vccio="3.3V"): assert vccio in ["2.5V", "3.3V"] Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _get_io(vccio), _connectors, toolchain="vivado") self.add_platform_command("""