From 982038508ea9647eaf40bbe643f2fa42b7cbf61d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 28 Dec 2023 19:56:45 +0100
Subject: [PATCH] alinx_axau15/PCIe: Switch to Gen3/128-bit for now
 (configuration used on others Ultrascale+ Gen3 X4 boards).

---
 litex_boards/targets/alinx_axau15.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex_boards/targets/alinx_axau15.py b/litex_boards/targets/alinx_axau15.py
index 4610b60..fbd8986 100755
--- a/litex_boards/targets/alinx_axau15.py
+++ b/litex_boards/targets/alinx_axau15.py
@@ -83,8 +83,8 @@ class BaseSoC(SoCCore):
         # PCIe -------------------------------------------------------------------------------------
         if with_pcie:
             self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
-                speed      = "gen4",
-                data_width = 256,
+                speed      = "gen3",
+                data_width = 128,
                 bar0_size  = 0x20000)
             self.add_pcie(phy=self.pcie_phy, ndmas=1)