diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py
index 190096d..902089d 100755
--- a/litex_boards/targets/icebreaker.py
+++ b/litex_boards/targets/icebreaker.py
@@ -157,10 +157,9 @@ class BaseSoC(SoCCore):
             if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
                 self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
 
-        ledsignals = Signal(2)
-        self.submodules.leds = GPIOOut(ledsignals)
-        self.comb += platform.request("user_ledr_n").eq(ledsignals[0])
-        self.comb += platform.request("user_ledg_n").eq(ledsignals[1])
+        self.submodules.leds = GPIOOut(Cat(
+            platform.request("user_ledr_n"),
+            platform.request("user_ledg_n")))
         self.add_csr("leds")
 
         # self.add_memory_region("rom", 0x2001a000, 16 * 1024 * 1024 - 0x1a000, type="cached+linker")