From 99f4f97f00915c27d99c56d8dd323899c22ed691 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 16 Nov 2021 17:41:26 +0100 Subject: [PATCH] efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target. --- .../efinix_trion_t120_bga576_dev_kit.py | 136 +++++++++++++++++- 1 file changed, 132 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index 1ec2272..f01d831 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -118,10 +118,138 @@ class BaseSoC(SoCCore): platform.toolchain.excluded_ios.append(dram_pll_refclk) self.platform.toolchain.additional_sdc_commands.append(f"create_clock -period {1e9/50e6} dram_pll_refclk") - block = {"type" : "DRAM"} - platform.toolchain.ifacewriter.xml_blocks.append(block) - block = {"type" : "PLL_DRAM"} - platform.toolchain.ifacewriter.blocks.append(block) + from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock + import xml.etree.ElementTree as et + + class PLLDRAMBlock(InterfaceWriterBlock): + @staticmethod + def generate(): + return """ +design.create_block("dram_pll", block_type="PLL") +design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL") +design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0") +design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL") +design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL") +design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL") +design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL") +calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"}) +""" + platform.toolchain.ifacewriter.blocks.append(PLLDRAMBlock()) + + class DRAMXMLBlock(InterfaceWriterXMLBlock): + @staticmethod + def generate(root, namespaces): + # CHECKME: Switch to DDRDesignService? + ddr_info = root.find("efxpt:ddr_info", namespaces) + + ddr = et.SubElement(ddr_info, "efxpt:ddr", + name = "ddr_inst1", + ddr_def = "DDR_0", + cs_preset_id = "173", + cs_mem_type = "LPDDR3", + cs_ctrl_width = "x32", + cs_dram_width = "x32", + cs_dram_density = "8G", + cs_speedbin = "800", + target0_enable = "true", + target1_enable = "false", + ctrl_type = "ena_user_rst" + ) + + gen_pin_target0 = et.SubElement(ddr, "efxpt:gen_pin_target0") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wdata", type_name=f"WDATA_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wready", type_name=f"WREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wid", type_name=f"WID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bready", type_name=f"BREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rdata", type_name=f"RDATA_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aid", type_name=f"AID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bvalid", type_name=f"BVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rlast", type_name=f"RLAST_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bid", type_name=f"BID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_asize", type_name=f"ASIZE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_atype", type_name=f"ATYPE_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aburst", type_name=f"ABURST_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wvalid", type_name=f"WVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wlast", type_name=f"WLAST_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aaddr", type_name=f"AADDR_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rid", type_name=f"RID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_avalid", type_name=f"AVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rvalid", type_name=f"RVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alock", type_name=f"ALOCK_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rready", type_name=f"RREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rresp", type_name=f"RRESP_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wstrb", type_name=f"WSTRB_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aready", type_name=f"AREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alen", type_name=f"ALEN_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="axi_clk", type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false") + + gen_pin_target1 = et.SubElement(ddr, "efxpt:gen_pin_target1") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wdata", type_name=f"WDATA_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wready", type_name=f"WREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wid", type_name=f"WID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bready", type_name=f"BREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rdata", type_name=f"RDATA_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aid", type_name=f"AID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bvalid", type_name=f"BVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rlast", type_name=f"RLAST_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bid", type_name=f"BID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_asize", type_name=f"ASIZE_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_atype", type_name=f"ATYPE_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aburst", type_name=f"ABURST_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wvalid", type_name=f"WVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wlast", type_name=f"WLAST_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aaddr", type_name=f"AADDR_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rid", type_name=f"RID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_avalid", type_name=f"AVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rvalid", type_name=f"RVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alock", type_name=f"ALOCK_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rready", type_name=f"RREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rresp", type_name=f"RRESP_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wstrb", type_name=f"WSTRB_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aready", type_name=f"AREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alen", type_name=f"ALEN_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="axi_clk", type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false") + + gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config") + et.SubElement(gen_pin_config, "efxpt:pin", name="ddr_inst1_CFG_SEQ_RST", type_name="CFG_SEQ_RST", is_bus="false") + et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SCL_IN", is_bus="false") + et.SubElement(gen_pin_config, "efxpt:pin", name="ddr_inst1_CFG_SEQ_START", type_name="CFG_SEQ_START", is_bus="false") + et.SubElement(gen_pin_config, "efxpt:pin", name="ddr_inst1_RSTN", type_name="RSTN", is_bus="false") + et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SDA_IN", is_bus="false") + et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SDA_OEN", is_bus="false") + + cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga") + et.SubElement(cs_fpga, "efxpt:param", name="FPGA_ITERM", value="120", value_type="str") + et.SubElement(cs_fpga, "efxpt:param", name="FPGA_OTERM", value="34", value_type="str") + + cs_memory = et.SubElement(ddr, "efxpt:cs_memory") + et.SubElement(cs_memory, "efxpt:param", name="RTT_NOM", value="RZQ/2", value_type="str") + et.SubElement(cs_memory, "efxpt:param", name="MEM_OTERM", value="40", value_type="str") + et.SubElement(cs_memory, "efxpt:param", name="CL", value="RL=6/WL=3", value_type="str") + + timing = et.SubElement(ddr, "efxpt:cs_memory_timing") + et.SubElement(timing, "efxpt:param", name="tRAS", value="42.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tRC", value="60.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tRP", value="18.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tRCD", value="18.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tREFI", value="3.900", value_type="float") + et.SubElement(timing, "efxpt:param", name="tRFC", value="210.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tRTP", value="10.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tWTR", value="10.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tRRD", value="10.000", value_type="float") + et.SubElement(timing, "efxpt:param", name="tFAW", value="50.000", value_type="float") + + cs_control = et.SubElement(ddr, "efxpt:cs_control") + et.SubElement(cs_control, "efxpt:param", name="AMAP", value="ROW-COL_HIGH-BANK-COL_LOW", value_type="str") + et.SubElement(cs_control, "efxpt:param", name="EN_AUTO_PWR_DN", value="Off", value_type="str") + et.SubElement(cs_control, "efxpt:param", name="EN_AUTO_SELF_REF", value="No", value_type="str") + + cs_gate_delay = et.SubElement(ddr, "efxpt:cs_gate_delay") + et.SubElement(cs_gate_delay, "efxpt:param", name="EN_DLY_OVR", value="No", value_type="str") + et.SubElement(cs_gate_delay, "efxpt:param", name="GATE_C_DLY", value="3", value_type="int") + et.SubElement(cs_gate_delay, "efxpt:param", name="GATE_F_DLY", value="0", value_type="int") + + platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock()) # DRAM Rst. # ---------